From patchwork Fri Oct 14 05:43:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118178 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 475C1A00C2; Fri, 14 Oct 2022 07:43:26 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2DF274014F; Fri, 14 Oct 2022 07:43:26 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7E2E2400D4 for ; Fri, 14 Oct 2022 07:43:24 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29E2JJTn005854 for ; Thu, 13 Oct 2022 22:43:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=W4/tu6znYaHHFmyK/HVPUbcVleo22+D72UL6Q7Asz80=; b=VXw7MA2/bDWYk2e4zTlE/G3wV2Up5b3HEzVtBynNXKGG0v7c8yDoCG6MB6fCmwownDm9 yZJr+R6w5NMkGV48UXGXKo89fLs/WtNVDcH0s431mF6qzwq+ionuTFPLwgA3QmGlEbDd ghI2FIeOLZQh4jbMxjiAyN8hctmAxmEQMOyUt9DcKl2anG+k4tFXXJh3y7HBWpkSwr63 siIhir3UDCNIH6zSF3jcPDfe1agl1nvh9com4jXxQQxULZNzXTPPDd42JAnBkM6vlYl3 Uy1UWvRz1/MxDVyLruH5Dr5HPLeKjSE4NI3N4aTbiXsC8rPP9Thb8bHRXelviGRHr/3E uA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3k6xvp0k5v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 13 Oct 2022 22:43:23 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 13 Oct 2022 22:43:21 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 13 Oct 2022 22:43:21 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 9BD2F3F7048; Thu, 13 Oct 2022 22:43:19 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Sathesh Edara Subject: [PATCH v3 01/13] common/cnxk: set MTU size on SDP based on SoC type Date: Fri, 14 Oct 2022 11:13:05 +0530 Message-ID: <20221014054317.1151306-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221011120135.45846-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: RcqdZVME_YezkByZSMpCM-KoJtygO2Tj X-Proofpoint-GUID: RcqdZVME_YezkByZSMpCM-KoJtygO2Tj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_02,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sathesh Edara Set maximum frame size on SDP NIX side to 16KB for T93 A0-B0, F95N A0 and F95O A0 SOC type. Rest of the SoCs SDP NIX to 64KB. Signed-off-by: Sathesh Edara --- v3: - Fix commit message in patch 9/13 v2: - Add fixes line in patch 1/13 - Squash patch 8/13 to 7/13 as 7/13 is the patch that introduced the bug - Add another patch to handle HARD SA expiry event for outbound inline. drivers/common/cnxk/hw/nix.h | 1 + drivers/common/cnxk/roc_errata.h | 8 ++++++++ drivers/common/cnxk/roc_model.h | 12 ++++++++++++ drivers/common/cnxk/roc_nix.c | 5 ++++- 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index a5352644ca..425c335bf3 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -2118,6 +2118,7 @@ struct nix_lso_format { #define NIX_CN9K_MAX_HW_FRS 9212UL #define NIX_LBK_MAX_HW_FRS 65535UL #define NIX_SDP_MAX_HW_FRS 65535UL +#define NIX_SDP_16K_HW_FRS 16380UL #define NIX_RPM_MAX_HW_FRS 16380UL #define NIX_MIN_HW_FRS 60UL diff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h index d3b32f1786..a39796e894 100644 --- a/drivers/common/cnxk/roc_errata.h +++ b/drivers/common/cnxk/roc_errata.h @@ -90,4 +90,12 @@ roc_errata_nix_no_meta_aura(void) return roc_model_is_cn10ka_a0(); } +/* Errata IPBUNIXTX-35039 */ +static inline bool +roc_errata_nix_sdp_send_has_mtu_size_16k(void) +{ + return (roc_model_is_cnf95xxn_a0() || roc_model_is_cnf95xxo_a0() || + roc_model_is_cn96_a0() || roc_model_is_cn96_b0()); +} + #endif /* _ROC_ERRATA_H_ */ diff --git a/drivers/common/cnxk/roc_model.h b/drivers/common/cnxk/roc_model.h index 57a8af06fc..1985dd771d 100644 --- a/drivers/common/cnxk/roc_model.h +++ b/drivers/common/cnxk/roc_model.h @@ -140,6 +140,12 @@ roc_model_is_cn96_ax(void) return (roc_model->flag & ROC_MODEL_CN96xx_Ax); } +static inline uint64_t +roc_model_is_cn96_b0(void) +{ + return (roc_model->flag & ROC_MODEL_CN96xx_B0); +} + static inline uint64_t roc_model_is_cn96_cx(void) { @@ -170,6 +176,12 @@ roc_model_is_cnf95xxn_b0(void) return roc_model->flag & ROC_MODEL_CNF95xxN_B0; } +static inline uint64_t +roc_model_is_cnf95xxo_a0(void) +{ + return roc_model->flag & ROC_MODEL_CNF95xxO_A0; +} + static inline uint16_t roc_model_is_cn95xxn_a0(void) { diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 4bb306b60e..8fd8ec8461 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -127,8 +127,11 @@ roc_nix_max_pkt_len(struct roc_nix *roc_nix) { struct nix *nix = roc_nix_to_nix_priv(roc_nix); - if (roc_nix_is_sdp(roc_nix)) + if (roc_nix_is_sdp(roc_nix)) { + if (roc_errata_nix_sdp_send_has_mtu_size_16k()) + return NIX_SDP_16K_HW_FRS; return NIX_SDP_MAX_HW_FRS; + } if (roc_model_is_cn9k()) return NIX_CN9K_MAX_HW_FRS; From patchwork Fri Oct 14 05:43:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118179 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AFDD1A00C2; Fri, 14 Oct 2022 07:43:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 13B8642C0D; Fri, 14 Oct 2022 07:43:29 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 102AE42C0B for ; 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Thu, 13 Oct 2022 22:43:26 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 13 Oct 2022 22:43:24 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 13 Oct 2022 22:43:24 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 674743F7058; Thu, 13 Oct 2022 22:43:22 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v3 02/13] common/cnxk: add devargs for soft expiry poll frequency Date: Fri, 14 Oct 2022 11:13:06 +0530 Message-ID: <20221014054317.1151306-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014054317.1151306-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221014054317.1151306-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: Q-X5yBwb2xT5u3vDt39IrKeTWLbyN5Pp X-Proofpoint-GUID: Q-X5yBwb2xT5u3vDt39IrKeTWLbyN5Pp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_02,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support to override soft expiry poll frequency via devargs. Also provide helper API to indicate reassembly support on a chip and documentation for devargs that are already present. Fixes: 780b9c89241b ("net/cnxk: support zero AURA for inline meta") Signed-off-by: Nithin Dabilpuram --- doc/guides/nics/cnxk.rst | 39 +++++++++++++++++++++++++++ drivers/common/cnxk/roc_nix_inl.c | 7 +++++ drivers/common/cnxk/roc_nix_inl.h | 3 ++- drivers/common/cnxk/roc_nix_inl_dev.c | 4 +-- drivers/common/cnxk/version.map | 1 + drivers/net/cnxk/cnxk_ethdev_sec.c | 17 +++++++++--- 6 files changed, 65 insertions(+), 6 deletions(-) diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst index a1e3a4a965..7da6cb3967 100644 --- a/doc/guides/nics/cnxk.rst +++ b/doc/guides/nics/cnxk.rst @@ -494,6 +494,45 @@ Runtime Config Options for inline device With the above configuration, application can enable inline IPsec processing for inbound SA with max SPI of 128 for traffic aggregated on inline device. +- ``Count of meta buffers for inline inbound IPsec second pass`` + + Number of meta buffers allocated for inline inbound IPsec second pass can + be specified by ``nb_meta_bufs`` ``devargs`` parameter. Default value is + computed runtime based on pkt mbuf pools created and in use. Number of meta + buffers should be at least equal to aggregated number of packet buffers of all + packet mbuf pools in use by Inline IPsec enabled ethernet devices. + + For example:: + + -a 0002:1d:00.0,nb_meta_bufs=1024 + + With the above configuration, PMD would enable inline IPsec processing + for inbound with 1024 meta buffers available for second pass. + +- ``Meta buffer size for inline inbound IPsec second pass`` + + Size of meta buffer allocated for inline inbound IPsec second pass can + be specified by ``meta_buf_sz`` ``devargs`` parameter. Default value is + computed runtime based on pkt mbuf pools created and in use. + + For example:: + + -a 0002:1d:00.0,meta_buf_sz=512 + + With the above configuration, PMD would allocate meta buffers of size 512 for + inline inbound IPsec processing second pass. + +- ``Inline Outbound soft expiry poll frequency in usec`` (default ``100``) + + Soft expiry poll frequency for Inline Outbound sessions can be specified by + ``soft_exp_poll_freq`` ``devargs`` parameter. + + For example:: + + -a 0002:1d:00.0,soft_exp_poll_freq=1000 + + With the above configuration, driver would poll for soft expiry events every + 1000 usec. Debugging Options ----------------- diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index cdf31b1f0c..213d71e684 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -480,6 +480,13 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable) return mbox_process(mbox); } +bool +roc_nix_has_reass_support(struct roc_nix *nix) +{ + PLT_SET_USED(nix); + return !!roc_model_is_cn10ka(); +} + int roc_nix_inl_inb_init(struct roc_nix *roc_nix) { diff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h index 019cf6d28b..c537262819 100644 --- a/drivers/common/cnxk/roc_nix_inl.h +++ b/drivers/common/cnxk/roc_nix_inl.h @@ -183,7 +183,7 @@ struct roc_nix_inl_dev { uint16_t wqe_skip; uint8_t spb_drop_pc; uint8_t lpb_drop_pc; - bool set_soft_exp_poll; + uint32_t soft_exp_poll_freq; /* Polling disabled if 0 */ uint32_t nb_meta_bufs; uint32_t meta_buf_sz; /* End of input parameters */ @@ -229,6 +229,7 @@ int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool inb_inl_dev); int __roc_api roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool ena); int __roc_api roc_nix_inl_meta_aura_check(struct roc_nix_rq *rq); +bool __roc_api roc_nix_has_reass_support(struct roc_nix *nix); /* NIX Inline Outbound API */ int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix); diff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c index 4fe7b5180b..c3d94dd0da 100644 --- a/drivers/common/cnxk/roc_nix_inl_dev.c +++ b/drivers/common/cnxk/roc_nix_inl_dev.c @@ -789,7 +789,6 @@ nix_inl_outb_poll_thread_setup(struct nix_inl_dev *inl_dev) soft_exp_consumer_cnt = 0; soft_exp_poll_thread_exit = false; - inl_dev->soft_exp_poll_freq = 100; rc = plt_ctrl_thread_create(&inl_dev->soft_exp_poll_thread, "OUTB_SOFT_EXP_POLL_THREAD", NULL, nix_inl_outb_poll_thread, inl_dev); @@ -839,10 +838,11 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev) inl_dev->wqe_skip = roc_inl_dev->wqe_skip; inl_dev->spb_drop_pc = NIX_AURA_DROP_PC_DFLT; inl_dev->lpb_drop_pc = NIX_AURA_DROP_PC_DFLT; - inl_dev->set_soft_exp_poll = roc_inl_dev->set_soft_exp_poll; + inl_dev->set_soft_exp_poll = !!roc_inl_dev->soft_exp_poll_freq; inl_dev->nb_rqs = inl_dev->is_multi_channel ? 1 : PLT_MAX_ETHPORTS; inl_dev->nb_meta_bufs = roc_inl_dev->nb_meta_bufs; inl_dev->meta_buf_sz = roc_inl_dev->meta_buf_sz; + inl_dev->soft_exp_poll_freq = roc_inl_dev->soft_exp_poll_freq; if (roc_inl_dev->spb_drop_pc) inl_dev->spb_drop_pc = roc_inl_dev->spb_drop_pc; diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index e935f17c28..e2c6a223ea 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -135,6 +135,7 @@ INTERNAL { roc_nix_get_pf_func; roc_nix_get_vf; roc_nix_get_vwqe_interval; + roc_nix_has_reass_support; roc_nix_inl_cb_register; roc_nix_inl_cb_unregister; roc_nix_inl_ctx_write; diff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c index 9304b1465d..8bec9acb54 100644 --- a/drivers/net/cnxk/cnxk_ethdev_sec.c +++ b/drivers/net/cnxk/cnxk_ethdev_sec.c @@ -12,6 +12,10 @@ #define CNXK_INL_CPT_CHANNEL "inl_cpt_channel" #define CNXK_NIX_INL_NB_META_BUFS "nb_meta_bufs" #define CNXK_NIX_INL_META_BUF_SZ "meta_buf_sz" +#define CNXK_NIX_SOFT_EXP_POLL_FREQ "soft_exp_poll_freq" + +/* Default soft expiry poll freq in usec */ +#define CNXK_NIX_SOFT_EXP_POLL_FREQ_DFLT 100 struct inl_cpt_channel { bool is_multi_channel; @@ -263,6 +267,7 @@ static int nix_inl_parse_devargs(struct rte_devargs *devargs, struct roc_nix_inl_dev *inl_dev) { + uint32_t soft_exp_poll_freq = CNXK_NIX_SOFT_EXP_POLL_FREQ_DFLT; uint32_t ipsec_in_max_spi = BIT(8) - 1; uint32_t ipsec_in_min_spi = 0; struct inl_cpt_channel cpt_channel; @@ -292,6 +297,8 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, &nb_meta_bufs); rte_kvargs_process(kvlist, CNXK_NIX_INL_META_BUF_SZ, &parse_val_u32, &meta_buf_sz); + rte_kvargs_process(kvlist, CNXK_NIX_SOFT_EXP_POLL_FREQ, + &parse_val_u32, &soft_exp_poll_freq); rte_kvargs_free(kvlist); null_devargs: @@ -303,6 +310,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs, inl_dev->is_multi_channel = cpt_channel.is_multi_channel; inl_dev->nb_meta_bufs = nb_meta_bufs; inl_dev->meta_buf_sz = meta_buf_sz; + inl_dev->soft_exp_poll_freq = soft_exp_poll_freq; return 0; exit: return -EINVAL; @@ -390,7 +398,6 @@ cnxk_nix_inl_dev_probe(struct rte_pci_driver *pci_drv, wqe_skip = RTE_ALIGN_CEIL(sizeof(struct rte_mbuf), ROC_CACHE_LINE_SZ); wqe_skip = wqe_skip / ROC_CACHE_LINE_SZ; inl_dev->wqe_skip = wqe_skip; - inl_dev->set_soft_exp_poll = true; rc = roc_nix_inl_dev_init(inl_dev); if (rc) { plt_err("Failed to init nix inl device, rc=%d(%s)", rc, @@ -425,5 +432,9 @@ RTE_PMD_REGISTER_KMOD_DEP(cnxk_nix_inl, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(cnxk_nix_inl, CNXK_NIX_INL_SELFTEST "=1" - CNXK_NIX_INL_IPSEC_IN_MAX_SPI "=<1-65535>" - CNXK_INL_CPT_CHANNEL "=<1-4095>/<1-4095>"); + CNXK_NIX_INL_IPSEC_IN_MIN_SPI "=<1-U32_MAX>" + CNXK_NIX_INL_IPSEC_IN_MAX_SPI "=<1-U32_MAX>" + CNXK_INL_CPT_CHANNEL "=<1-4095>/<1-4095>" + CNXK_NIX_INL_NB_META_BUFS "=<1-U32_MAX>" + CNXK_NIX_INL_META_BUF_SZ "=<1-U32_MAX>" + CNXK_NIX_SOFT_EXP_POLL_FREQ "=<0-U32_MAX>"); From patchwork Fri Oct 14 05:43:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118180 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E5C90A00C2; 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Thu, 13 Oct 2022 22:43:28 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 13 Oct 2022 22:43:27 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 13 Oct 2022 22:43:27 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id E4A6B3F7048; Thu, 13 Oct 2022 22:43:24 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Subject: [PATCH v3 03/13] net/cnxk: fix later skip to include mbuf priv Date: Fri, 14 Oct 2022 11:13:07 +0530 Message-ID: <20221014054317.1151306-3-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014054317.1151306-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221014054317.1151306-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: qeXuhSP_Uu5x_Ip22_qySjeqpiQ0eSFv X-Proofpoint-GUID: qeXuhSP_Uu5x_Ip22_qySjeqpiQ0eSFv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_02,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Fix later skip to include mbuf priv data as mbuf->buf_addr is populated based on calculation including per-mbuf priv area. Fixes: 706eeae60757 ("net/cnxk: add multi-segment Rx for CN10K") cc: stable@dpdk.org Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_rx.h | 4 +++- drivers/net/cnxk/cnxk_ethdev.c | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index 46488d442e..cf390a0361 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -682,6 +682,7 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, uint64_t rearm, const uint16_t flags) { const rte_iova_t *iova_list; + uint16_t later_skip = 0; struct rte_mbuf *head; const rte_iova_t *eol; uint8_t nb_segs; @@ -720,10 +721,11 @@ nix_cqe_xtract_mseg(const union nix_rx_parse_u *rx, struct rte_mbuf *mbuf, nb_segs--; rearm = rearm & ~0xFFFF; + later_skip = (uintptr_t)mbuf->buf_addr - (uintptr_t)mbuf; head = mbuf; while (nb_segs) { - mbuf->next = ((struct rte_mbuf *)*iova_list) - 1; + mbuf->next = (struct rte_mbuf *)(*iova_list - later_skip); mbuf = mbuf->next; RTE_MEMPOOL_CHECK_COOKIES(mbuf->pool, (void **)&mbuf, 1, 1); diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 71c3f1666b..bf1585fe67 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -680,7 +680,7 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid, first_skip += RTE_PKTMBUF_HEADROOM; first_skip += rte_pktmbuf_priv_size(lpb_pool); rq->first_skip = first_skip; - rq->later_skip = sizeof(struct rte_mbuf); + rq->later_skip = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mp); rq->lpb_size = lpb_pool->elt_size; if (roc_errata_nix_no_meta_aura()) rq->lpb_drop_ena = !(dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY); From patchwork Fri Oct 14 05:43:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118181 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 271D8A00C2; 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Thu, 13 Oct 2022 22:43:31 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 13 Oct 2022 22:43:30 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 13 Oct 2022 22:43:30 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id B63423F7058; Thu, 13 Oct 2022 22:43:27 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Pavan Nikhilesh , "Shijith Thotton" CC: , Subject: [PATCH v3 04/13] net/cnxk: use NIX Tx offset for cn10kb Date: Fri, 14 Oct 2022 11:13:08 +0530 Message-ID: <20221014054317.1151306-4-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014054317.1151306-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221014054317.1151306-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: LKXVcK_t5bxZHTLD67tsR-d5eiceI8bx X-Proofpoint-GUID: LKXVcK_t5bxZHTLD67tsR-d5eiceI8bx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_02,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In outbound inline case, use NIX Tx offset instead of NIX Tx address for CN103XX as per new instruction format. Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_constants.h | 1 + drivers/event/cnxk/cn10k_worker.h | 3 +++ drivers/net/cnxk/cn10k_ethdev.c | 6 ++++++ drivers/net/cnxk/cn10k_ethdev.h | 3 ++- drivers/net/cnxk/cn10k_ethdev_sec.c | 2 ++ drivers/net/cnxk/cn10k_tx.h | 4 ++-- 6 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/common/cnxk/roc_constants.h b/drivers/common/cnxk/roc_constants.h index c693dde62e..0495965daa 100644 --- a/drivers/common/cnxk/roc_constants.h +++ b/drivers/common/cnxk/roc_constants.h @@ -12,6 +12,7 @@ /* [CN10K, .) */ #define ROC_LMT_LINE_SZ 128 #define ROC_NUM_LMT_LINES 2048 +#define ROC_LMT_LINES_PER_STR_LOG2 4 #define ROC_LMT_LINES_PER_CORE_LOG2 5 #define ROC_LMT_LINE_SIZE_LOG2 7 #define ROC_LMT_BASE_PER_CORE_LOG2 \ diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h index 7a82dd352a..75a2ff244a 100644 --- a/drivers/event/cnxk/cn10k_worker.h +++ b/drivers/event/cnxk/cn10k_worker.h @@ -595,6 +595,9 @@ cn10k_sso_tx_one(struct cn10k_sso_hws *ws, struct rte_mbuf *m, uint64_t *cmd, ws->gw_rdata = roc_sso_hws_head_wait(ws->base); cn10k_sso_txq_fc_wait(txq); + if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec) + cn10k_nix_sec_fc_wait_one(txq); + roc_lmt_submit_steorl(lmt_id, pa); if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) { diff --git a/drivers/net/cnxk/cn10k_ethdev.c b/drivers/net/cnxk/cn10k_ethdev.c index 0b33b3a496..4658713591 100644 --- a/drivers/net/cnxk/cn10k_ethdev.c +++ b/drivers/net/cnxk/cn10k_ethdev.c @@ -538,6 +538,9 @@ cn10k_nix_reassembly_capability_get(struct rte_eth_dev *eth_dev, int rc = -ENOTSUP; RTE_SET_USED(eth_dev); + if (!roc_nix_has_reass_support(&dev->nix)) + return -ENOTSUP; + if (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) { reassembly_capa->timeout_ms = 60 * 1000; reassembly_capa->max_frags = 4; @@ -565,6 +568,9 @@ cn10k_nix_reassembly_conf_set(struct rte_eth_dev *eth_dev, struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); int rc = 0; + if (!roc_nix_has_reass_support(&dev->nix)) + return -ENOTSUP; + if (!conf->flags) { /* Clear offload flags on disable */ dev->rx_offload_flags &= ~NIX_RX_REAS_F; diff --git a/drivers/net/cnxk/cn10k_ethdev.h b/drivers/net/cnxk/cn10k_ethdev.h index d0a5b136e3..948c8348ad 100644 --- a/drivers/net/cnxk/cn10k_ethdev.h +++ b/drivers/net/cnxk/cn10k_ethdev.h @@ -75,7 +75,8 @@ struct cn10k_sec_sess_priv { uint16_t partial_len : 10; uint16_t chksum : 2; uint16_t dec_ttl : 1; - uint16_t rsvd : 3; + uint16_t nixtx_off : 1; + uint16_t rsvd : 2; }; uint64_t u64; diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 6de4a284da..3ca707f038 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -798,6 +798,8 @@ cn10k_eth_sec_session_create(void *device, sess_priv.chksum = (!ipsec->options.ip_csum_enable << 1 | !ipsec->options.l4_csum_enable); sess_priv.dec_ttl = ipsec->options.dec_ttl; + if (roc_model_is_cn10kb_a0()) + sess_priv.nixtx_off = 1; /* Pointer from eth_sec -> outb_sa */ eth_sec->sa = outb_sa; diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 36fa96f83f..d375183f90 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -397,7 +397,7 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1, /* DLEN passed is excluding L2 HDR */ pkt_len -= l2_len; } - w0 |= nixtx; + w0 |= sess_priv.nixtx_off ? ((((int64_t)nixtx - (int64_t)dptr) & 0xFFFFF) << 32) : nixtx; /* CPT word 0 and 1 */ cmd01 = vdupq_n_u64(0); cmd01 = vsetq_lane_u64(w0, cmd01, 0); @@ -539,7 +539,7 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr, sg->seg1_size = pkt_len + dlen_adj; pkt_len -= l2_len; } - w0 |= nixtx; + w0 |= sess_priv.nixtx_off ? ((((int64_t)nixtx - (int64_t)dptr) & 0xFFFFF) << 32) : nixtx; /* CPT word 0 and 1 */ cmd01 = vdupq_n_u64(0); cmd01 = vsetq_lane_u64(w0, cmd01, 0); From patchwork Fri Oct 14 05:43:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118182 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D5F5BA00C2; Fri, 14 Oct 2022 07:43:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B747842C1C; Fri, 14 Oct 2022 07:43:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 3609842C28 for ; Fri, 14 Oct 2022 07:43:35 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29E2JnDS006062 for ; Thu, 13 Oct 2022 22:43:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Zsc24S5RVFmtiGdiLW0SE77B+10vXl3e7NZnG11bTV0=; b=k/fx8a89jGIN1VhEtfhIb1O4A6WQQFJOVBJv+XFsbBix3LqH8jj7avW3iNq5pixR+NTZ dHYbhY+P2JOUHdazc5Ox6MV6WWBZALp+YcrebS4sckEeBYRvQsU5wmK62++jGZINoXn0 HEUcPsgLFLpUCMo0v8DsWz4anyc8q8nnO1ijm270y+K1cFNPy7ieZC+CJdFOKu+DXqZX q6mgjTbrSWRg79xa89NrNJStMRQQEGHLnVPxiNglqFNY82XK57dJdImeIbEdclTB93UD fNnPpKn04FblS/ji31qSUS9Xao8+7S/ZPsm+P+g1JaRUAp74EuARD1N0kiYtcxx/sBUu ew== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3k6xvp0k6q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 13 Oct 2022 22:43:34 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 13 Oct 2022 22:43:32 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 13 Oct 2022 22:43:32 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id B421B3F7048; Thu, 13 Oct 2022 22:43:30 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v3 05/13] common/cnxk: fix RQ mask config for cn10kb chip Date: Fri, 14 Oct 2022 11:13:09 +0530 Message-ID: <20221014054317.1151306-5-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014054317.1151306-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221014054317.1151306-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: e5TtGtQYrU-9GNelxOHAdD24StFCBaRg X-Proofpoint-GUID: e5TtGtQYrU-9GNelxOHAdD24StFCBaRg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_02,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org RQ mask config needs to enable SPB_ENA in order for Zero for being able to override it with Meta aura. Also fix flow control config to catch invalid rxchan config errors. Fixes: ddf955d3917e ("common/cnxk: support CPT second pass") Fixes: da57d4589a6f ("common/cnxk: support NIX flow control") Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_nix_fc.c | 4 ++- drivers/common/cnxk/roc_nix_inl.c | 43 +++++++++++++++++-------------- 2 files changed, 26 insertions(+), 21 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c index f4cfa11c0f..033e17a4bf 100644 --- a/drivers/common/cnxk/roc_nix_fc.c +++ b/drivers/common/cnxk/roc_nix_fc.c @@ -52,8 +52,10 @@ nix_fc_rxchan_bpid_set(struct roc_nix *roc_nix, bool enable) req->bpid_per_chan = true; rc = mbox_process_msg(mbox, (void *)&rsp); - if (rc || (req->chan_cnt != rsp->chan_cnt)) + if (rc || (req->chan_cnt != rsp->chan_cnt)) { + rc = -EIO; goto exit; + } nix->chan_cnt = rsp->chan_cnt; for (i = 0; i < rsp->chan_cnt; i++) diff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c index 213d71e684..0da097c9e9 100644 --- a/drivers/common/cnxk/roc_nix_inl.c +++ b/drivers/common/cnxk/roc_nix_inl.c @@ -454,27 +454,29 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable) msk_req->rq_set.lpb_drop_ena = 0; msk_req->rq_set.spb_drop_ena = 0; msk_req->rq_set.xqe_drop_ena = 0; + msk_req->rq_set.spb_ena = 1; - msk_req->rq_mask.len_ol3_dis = ~(msk_req->rq_set.len_ol3_dis); - msk_req->rq_mask.len_ol4_dis = ~(msk_req->rq_set.len_ol4_dis); - msk_req->rq_mask.len_il3_dis = ~(msk_req->rq_set.len_il3_dis); + msk_req->rq_mask.len_ol3_dis = 0; + msk_req->rq_mask.len_ol4_dis = 0; + msk_req->rq_mask.len_il3_dis = 0; - msk_req->rq_mask.len_il4_dis = ~(msk_req->rq_set.len_il4_dis); - msk_req->rq_mask.csum_ol4_dis = ~(msk_req->rq_set.csum_ol4_dis); - msk_req->rq_mask.csum_il4_dis = ~(msk_req->rq_set.csum_il4_dis); + msk_req->rq_mask.len_il4_dis = 0; + msk_req->rq_mask.csum_ol4_dis = 0; + msk_req->rq_mask.csum_il4_dis = 0; - msk_req->rq_mask.lenerr_dis = ~(msk_req->rq_set.lenerr_dis); - msk_req->rq_mask.port_ol4_dis = ~(msk_req->rq_set.port_ol4_dis); - msk_req->rq_mask.port_il4_dis = ~(msk_req->rq_set.port_il4_dis); + msk_req->rq_mask.lenerr_dis = 0; + msk_req->rq_mask.port_ol4_dis = 0; + msk_req->rq_mask.port_il4_dis = 0; - msk_req->rq_mask.lpb_drop_ena = ~(msk_req->rq_set.lpb_drop_ena); - msk_req->rq_mask.spb_drop_ena = ~(msk_req->rq_set.spb_drop_ena); - msk_req->rq_mask.xqe_drop_ena = ~(msk_req->rq_set.xqe_drop_ena); + msk_req->rq_mask.lpb_drop_ena = 0; + msk_req->rq_mask.spb_drop_ena = 0; + msk_req->rq_mask.xqe_drop_ena = 0; + msk_req->rq_mask.spb_ena = 0; aura_handle = roc_npa_zero_aura_handle(); msk_req->ipsec_cfg1.spb_cpt_aura = roc_npa_aura_handle_to_aura(aura_handle); msk_req->ipsec_cfg1.rq_mask_enable = enable; - msk_req->ipsec_cfg1.spb_cpt_sizem1 = inl_cfg->buf_sz; + msk_req->ipsec_cfg1.spb_cpt_sizem1 = (inl_cfg->buf_sz >> 7) - 1; msk_req->ipsec_cfg1.spb_cpt_enable = enable; return mbox_process(mbox); @@ -544,13 +546,6 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix) idev->inl_cfg.refs++; } - if (roc_model_is_cn10kb_a0()) { - rc = nix_inl_rq_mask_cfg(roc_nix, true); - if (rc) { - plt_err("Failed to get rq mask rc=%d", rc); - return rc; - } - } nix->inl_inb_ena = true; return 0; } @@ -1043,6 +1038,14 @@ roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool enable) if (!idev) return -EFAULT; + if (roc_model_is_cn10kb_a0()) { + rc = nix_inl_rq_mask_cfg(roc_nix, true); + if (rc) { + plt_err("Failed to get rq mask rc=%d", rc); + return rc; + } + } + if (nix->inb_inl_dev) { if (!inl_rq || !idev->nix_inl_dev) return -EFAULT; From patchwork Fri Oct 14 05:43:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118183 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AC729A00C2; Fri, 14 Oct 2022 07:43:57 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B05D442C32; Fri, 14 Oct 2022 07:43:40 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 1390C42C29 for ; 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Thu, 13 Oct 2022 22:43:37 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 13 Oct 2022 22:43:35 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 13 Oct 2022 22:43:35 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 418C03F7058; Thu, 13 Oct 2022 22:43:33 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v3 06/13] common/cnxk: fix schedule weight update Date: Fri, 14 Oct 2022 11:13:10 +0530 Message-ID: <20221014054317.1151306-6-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014054317.1151306-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221014054317.1151306-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: Wtgi0wTVhLBmPvLQoVrm71EVcneZTImM X-Proofpoint-ORIG-GUID: Wtgi0wTVhLBmPvLQoVrm71EVcneZTImM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_01,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Each TX schedule config mail box supports maximum 20 register updates. This patch will send node weight updates in multiple mailbox when TM created with more than 20 scheduler nodes. Fixes: 464c9f919321 ("common/cnxk: support NIX TM dynamic update") Cc: ndabilpuram@marvell.com Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix_queue.c | 2 +- drivers/common/cnxk/roc_nix_tm_ops.c | 60 ++++++++++++++++++---------- 2 files changed, 41 insertions(+), 21 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 368f1a52f7..7318f26b57 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -916,7 +916,7 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) nb_sqb_bufs += NIX_SQB_LIST_SPACE; /* Clamp up the SQB count */ nb_sqb_bufs = PLT_MIN(roc_nix->max_sqb_count, - PLT_MAX(NIX_DEF_SQB, nb_sqb_bufs)); + (uint16_t)PLT_MAX(NIX_DEF_SQB, nb_sqb_bufs)); sq->nb_sqb_bufs = nb_sqb_bufs; sq->sqes_per_sqb_log2 = (uint16_t)plt_log2_u32(sqes_per_sqb); diff --git a/drivers/common/cnxk/roc_nix_tm_ops.c b/drivers/common/cnxk/roc_nix_tm_ops.c index 7036495ad8..4bf7b1e104 100644 --- a/drivers/common/cnxk/roc_nix_tm_ops.c +++ b/drivers/common/cnxk/roc_nix_tm_ops.c @@ -891,19 +891,29 @@ roc_nix_tm_node_parent_update(struct roc_nix *roc_nix, uint32_t node_id, TAILQ_FOREACH(sibling, list, node) { if (sibling->parent != node->parent) continue; - k += nix_tm_sw_xoff_prep(sibling, true, &req->reg[k], - &req->regval[k]); + k += nix_tm_sw_xoff_prep(sibling, true, &req->reg[k], &req->regval[k]); + if (k >= MAX_REGS_PER_MBOX_MSG) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + return rc; + k = 0; + req = mbox_alloc_msg_nix_txschq_cfg(mbox); + req->lvl = node->hw_lvl; + } + } + + if (k) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + return rc; + /* Update new weight for current node */ + req = mbox_alloc_msg_nix_txschq_cfg(mbox); } - req->num_regs = k; - rc = mbox_process(mbox); - if (rc) - return rc; - /* Update new weight for current node */ - req = mbox_alloc_msg_nix_txschq_cfg(mbox); req->lvl = node->hw_lvl; - req->num_regs = - nix_tm_sched_reg_prep(nix, node, req->reg, req->regval); + req->num_regs = nix_tm_sched_reg_prep(nix, node, req->reg, req->regval); rc = mbox_process(mbox); if (rc) return rc; @@ -916,19 +926,29 @@ roc_nix_tm_node_parent_update(struct roc_nix *roc_nix, uint32_t node_id, TAILQ_FOREACH(sibling, list, node) { if (sibling->parent != node->parent) continue; - k += nix_tm_sw_xoff_prep(sibling, false, &req->reg[k], - &req->regval[k]); + k += nix_tm_sw_xoff_prep(sibling, false, &req->reg[k], &req->regval[k]); + if (k >= MAX_REGS_PER_MBOX_MSG) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + return rc; + k = 0; + req = mbox_alloc_msg_nix_txschq_cfg(mbox); + req->lvl = node->hw_lvl; + } + } + + if (k) { + req->num_regs = k; + rc = mbox_process(mbox); + if (rc) + return rc; + /* XON Parent node */ + req = mbox_alloc_msg_nix_txschq_cfg(mbox); } - req->num_regs = k; - rc = mbox_process(mbox); - if (rc) - return rc; - /* XON Parent node */ - req = mbox_alloc_msg_nix_txschq_cfg(mbox); req->lvl = node->parent->hw_lvl; - req->num_regs = nix_tm_sw_xoff_prep(node->parent, false, - req->reg, req->regval); + req->num_regs = nix_tm_sw_xoff_prep(node->parent, false, req->reg, req->regval); rc = mbox_process(mbox); if (rc) return rc; From patchwork Fri Oct 14 05:43:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118184 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AE025A00C2; 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Thu, 13 Oct 2022 22:43:39 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 13 Oct 2022 22:43:37 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 13 Oct 2022 22:43:37 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id C8E193F706B; Thu, 13 Oct 2022 22:43:35 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v3 07/13] common/cnxk: sync NIX HW info mbox structure with kernel Date: Fri, 14 Oct 2022 11:13:11 +0530 Message-ID: <20221014054317.1151306-7-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014054317.1151306-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221014054317.1151306-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: RH0DiiRlM4ZMO-N-qWJwGlwB5aufe43i X-Proofpoint-GUID: RH0DiiRlM4ZMO-N-qWJwGlwB5aufe43i X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_02,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Sync nix_hw_info structure with kernel. Maintain default RR_QUANTUM for VF TL2 same as kernel to make equal distribution among all VFs. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_mbox.h | 8 +++++- drivers/common/cnxk/roc_nix.c | 9 ++++++- drivers/common/cnxk/roc_nix.h | 1 + drivers/common/cnxk/roc_nix_tm.c | 4 --- drivers/common/cnxk/roc_nix_tm_utils.c | 34 +++++++++++++++++++++----- 5 files changed, 44 insertions(+), 12 deletions(-) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index a47e6a8f3b..e8d4ae283d 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -1215,7 +1215,13 @@ struct nix_inline_ipsec_lf_cfg { struct nix_hw_info { struct mbox_msghdr hdr; uint16_t __io vwqe_delay; - uint16_t __io rsvd[15]; + uint16_t __io max_mtu; + uint16_t __io min_mtu; + uint32_t __io rpm_dwrr_mtu; + uint32_t __io sdp_dwrr_mtu; + uint32_t __io lbk_dwrr_mtu; + uint32_t __io rsvd32[1]; + uint64_t __io rsvd[15]; /* Add reserved fields for future expansion */ }; struct nix_bandprof_alloc_req { diff --git a/drivers/common/cnxk/roc_nix.c b/drivers/common/cnxk/roc_nix.c index 8fd8ec8461..2a320cc291 100644 --- a/drivers/common/cnxk/roc_nix.c +++ b/drivers/common/cnxk/roc_nix.c @@ -303,8 +303,15 @@ roc_nix_get_hw_info(struct roc_nix *roc_nix) mbox_alloc_msg_nix_get_hw_info(mbox); rc = mbox_process_msg(mbox, (void *)&hw_info); - if (rc == 0) + if (rc == 0) { nix->vwqe_interval = hw_info->vwqe_delay; + if (nix->lbk_link) + roc_nix->dwrr_mtu = hw_info->lbk_dwrr_mtu; + else if (nix->sdp_link) + roc_nix->dwrr_mtu = hw_info->sdp_dwrr_mtu; + else + roc_nix->dwrr_mtu = hw_info->rpm_dwrr_mtu; + } return rc; } diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 34cb2c717c..6636ee52c1 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -426,6 +426,7 @@ struct roc_nix { uint32_t ipsec_in_min_spi; uint32_t ipsec_in_max_spi; uint32_t ipsec_out_max_sa; + uint32_t dwrr_mtu; bool ipsec_out_sso_pffunc; bool custom_sa_action; /* End of input parameters */ diff --git a/drivers/common/cnxk/roc_nix_tm.c b/drivers/common/cnxk/roc_nix_tm.c index 81fa6b1d93..be8da714cd 100644 --- a/drivers/common/cnxk/roc_nix_tm.c +++ b/drivers/common/cnxk/roc_nix_tm.c @@ -256,10 +256,6 @@ nix_tm_node_add(struct roc_nix *roc_nix, struct nix_tm_node *node) if (node->weight > roc_nix_tm_max_sched_wt_get()) return NIX_ERR_TM_WEIGHT_EXCEED; - /* Maintain minimum weight */ - if (!node->weight) - node->weight = 1; - node->hw_lvl = nix_tm_lvl2nix(nix, lvl); node->rr_prio = 0xF; node->max_prio = UINT32_MAX; diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c index 193f9df5ff..d33e793664 100644 --- a/drivers/common/cnxk/roc_nix_tm_utils.c +++ b/drivers/common/cnxk/roc_nix_tm_utils.c @@ -644,9 +644,25 @@ nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node, return k; } +static inline int +nix_tm_default_rr_weight(struct nix *nix) +{ + struct roc_nix *roc_nix = nix_priv_to_roc_nix(nix); + uint32_t max_pktlen = roc_nix_max_pkt_len(roc_nix); + uint32_t weight; + + /* Reduce TX VTAG Insertions */ + max_pktlen -= 8; + weight = max_pktlen / roc_nix->dwrr_mtu; + if (max_pktlen % roc_nix->dwrr_mtu) + weight += 1; + + return weight; +} + uint8_t -nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node, - volatile uint64_t *reg, volatile uint64_t *regval) +nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node, volatile uint64_t *reg, + volatile uint64_t *regval) { uint64_t strict_prio = node->priority; uint32_t hw_lvl = node->hw_lvl; @@ -654,8 +670,14 @@ nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node, uint64_t rr_quantum; uint8_t k = 0; - /* For CN9K, weight needs to be converted to quantum */ - rr_quantum = nix_tm_weight_to_rr_quantum(node->weight); + /* If minimum weight not provided, then by default RR_QUANTUM + * should be in sync with kernel, i.e., single MTU value + */ + if (!node->weight) + rr_quantum = nix_tm_default_rr_weight(nix); + else + /* For CN9K, weight needs to be converted to quantum */ + rr_quantum = nix_tm_weight_to_rr_quantum(node->weight); /* For children to root, strict prio is default if either * device root is TL2 or TL1 Static Priority is disabled. @@ -666,8 +688,8 @@ nix_tm_sched_reg_prep(struct nix *nix, struct nix_tm_node *node, plt_tm_dbg("Schedule config node %s(%u) lvl %u id %u, " "prio 0x%" PRIx64 ", rr_quantum/rr_wt 0x%" PRIx64 " (%p)", - nix_tm_hwlvl2str(node->hw_lvl), schq, node->lvl, node->id, - strict_prio, rr_quantum, node); + nix_tm_hwlvl2str(node->hw_lvl), schq, node->lvl, node->id, strict_prio, + rr_quantum, node); switch (hw_lvl) { case NIX_TXSCH_LVL_SMQ: From patchwork Fri Oct 14 05:43:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118185 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 03058A00C2; Fri, 14 Oct 2022 07:44:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D7C0C42C3C; Fri, 14 Oct 2022 07:43:44 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id CA04542C16 for ; Fri, 14 Oct 2022 07:43:42 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29E2JGUq005517 for ; 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Thu, 13 Oct 2022 22:43:40 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 13 Oct 2022 22:43:40 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 4F29C3F7048; Thu, 13 Oct 2022 22:43:38 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v3 08/13] common/cnxk: set hysteresis bit to one Date: Fri, 14 Oct 2022 11:13:12 +0530 Message-ID: <20221014054317.1151306-8-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014054317.1151306-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221014054317.1151306-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 3jgRvGp6hWvwmYQtYOcK_wZUMvBdECY_ X-Proofpoint-GUID: 3jgRvGp6hWvwmYQtYOcK_wZUMvBdECY_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_02,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Satha Rao Setting non zero FC_HYST_BITS to reduce mesh traffic on HW. Signed-off-by: Satha Rao --- drivers/common/cnxk/roc_nix_queue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 7318f26b57..1cb1fd2101 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -940,7 +940,7 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) else aura.fc_stype = 0x3; /* STSTP */ aura.fc_addr = (uint64_t)sq->fc; - aura.fc_hyst_bits = 0; /* Store count on all updates */ + aura.fc_hyst_bits = 1; /* Store count on all updates */ rc = roc_npa_pool_create(&sq->aura_handle, blk_sz, nb_sqb_bufs, &aura, &pool, 0); if (rc) From patchwork Fri Oct 14 05:43:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118186 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5239AA00C2; Fri, 14 Oct 2022 07:44:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3305D42C4C; Fri, 14 Oct 2022 07:43:47 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id E5B8842C16 for ; Fri, 14 Oct 2022 07:43:45 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29E2JGUr005517 for ; Thu, 13 Oct 2022 22:43:45 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=OcTffw9i5m+6pSuB0oAy6WP6yxQyIT9fZ3SICWeUf6U=; b=KmE4p++pk4W4ECVzrliJnDn+1pAgtEyi1RP3pSFD2NrI3NBJeiTKwEaR9Ifrf/uiYkNQ jMbxcW1AnduN2FmsDJ/5ND2MW9sKJQNM7+NkwmiHGdYzBkRdRTRkI5KzusPuF5h6F0Ld NB4TIYrdInbKmKOyusip5Ajt2bgjTuGhfAEMppJkit9/q+n5zQcJcIh+ZSG0+Ha8qTFd FVm4iuXwXzXtCX43myyqedUusjRAvN99EOL/Bx92PbmwTT4FH9jsE5uHFSJcEwXIrWMu eynBtOW0oG3JbIXQ5gE11irFYmkwQclMIt2kdepwv0W7tFOq9hXqKMoWXpAVMOGFwuFW JA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3k6xvp0k7g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 13 Oct 2022 22:43:45 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 13 Oct 2022 22:43:43 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 13 Oct 2022 22:43:43 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id D7F5C3F7058; Thu, 13 Oct 2022 22:43:40 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Vamsi Attunuru Subject: [PATCH v3 09/13] net/cnxk: handle SA soft packet and byte expiry events Date: Fri, 14 Oct 2022 11:13:13 +0530 Message-ID: <20221014054317.1151306-9-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014054317.1151306-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221014054317.1151306-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: xilVK3wCwSSchNVhm-1OfeCN4M5UP1GK X-Proofpoint-GUID: xilVK3wCwSSchNVhm-1OfeCN4M5UP1GK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_02,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vamsi Attunuru Handle SA soft packet and byte expiry event for Inline outbound SA. Signed-off-by: Vamsi Attunuru --- drivers/net/cnxk/cn10k_ethdev_sec.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index 3ca707f038..ce1b10d885 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -428,7 +428,12 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args, uint32_t soft_exp_event) sa = (struct roc_ot_ipsec_outb_sa *)args; priv = roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(sa); desc.metadata = (uint64_t)priv->userdata; - desc.subtype = RTE_ETH_EVENT_IPSEC_SA_TIME_EXPIRY; + if (sa->w2.s.life_unit == ROC_IE_OT_SA_LIFE_UNIT_PKTS) + desc.subtype = + RTE_ETH_EVENT_IPSEC_SA_PKT_EXPIRY; + else + desc.subtype = + RTE_ETH_EVENT_IPSEC_SA_BYTE_EXPIRY; eth_dev = &rte_eth_devices[soft_exp_event >> 8]; rte_eth_dev_callback_process(eth_dev, RTE_ETH_EVENT_IPSEC, &desc); From patchwork Fri Oct 14 05:43:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118187 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DD425A00C2; Fri, 14 Oct 2022 07:44:22 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 278A942C52; Fri, 14 Oct 2022 07:43:50 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 982F142C52 for ; Fri, 14 Oct 2022 07:43:48 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29DJlnZv010292 for ; Thu, 13 Oct 2022 22:43:48 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=f5vrnSadAnc9Cg8X73VyVLGsK7alxFdJRwy8WBVetcY=; b=ZjH2iuEsjemQL8xQfYkHXtUlxX652zsCVH2XHTK5PkFdd15PngU2uble7y+wS7OeKzGb uIr6FUh1a26YVpp+P2ZjA/GN6Ou7tu/fLhBSUwyTWZtS0Q92/t4TLDn1pApD0Br8HPOV KjGcLepr9EQ8ph8MwnuMhCJ3cdO0j78ZwfK5NUIy2RxEp6irZm+P+brwm0DhYLG6F0IN /9hTwZNv2r4QkF0ReLk/V5hcBjzkQ/N3L435SEEko4uEYMuLabE8d5TVSo6p2mAamvzA 0afj2EO2+f3+08X5mFj82ixQ0kZUa9WoGo/xIUtt1BGvn8i4YazMyY2YdPebEFZn04f3 Lg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k6fwvcbg6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 13 Oct 2022 22:43:47 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 13 Oct 2022 22:43:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 13 Oct 2022 22:43:45 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id ABE0F3F7048; Thu, 13 Oct 2022 22:43:43 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v3 10/13] common/cnxk: sync mailbox for channel and bpid map Date: Fri, 14 Oct 2022 11:13:14 +0530 Message-ID: <20221014054317.1151306-10-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014054317.1151306-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221014054317.1151306-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: PF2eviZlfvLuBSyWwSCLRrKK33Ysa4dK X-Proofpoint-ORIG-GUID: PF2eviZlfvLuBSyWwSCLRrKK33Ysa4dK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_01,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori As per recent change in Linux-5.4.x, mailbox is updated to configure mapping between channel and BPID. Due to mbox mismatch, PFC was broken. Patch syncs mailbox definition for the same. Also fixes the PFC configuration issues. Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/roc_mbox.h | 6 +++--- drivers/common/cnxk/roc_nix.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index e8d4ae283d..d47808e5ef 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -1164,10 +1164,10 @@ struct nix_bp_cfg_req { /* bpid_per_chan = 1 assigns separate bp id for each channel */ }; -/* PF can be mapped to either CGX or LBK interface, - * so maximum 64 channels are possible. +/* PF can be mapped to either CGX or LBK or SDP interface, + * so maximum 256 channels are possible. */ -#define NIX_MAX_CHAN 64 +#define NIX_MAX_CHAN 256 #define NIX_CGX_MAX_CHAN 16 #define NIX_LBK_MAX_CHAN 1 struct nix_bp_cfg_rsp { diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h index 6636ee52c1..6654a2df78 100644 --- a/drivers/common/cnxk/roc_nix.h +++ b/drivers/common/cnxk/roc_nix.h @@ -436,7 +436,7 @@ struct roc_nix { bool rx_ptp_ena; uint16_t cints; -#define ROC_NIX_MEM_SZ (6 * 1024) +#define ROC_NIX_MEM_SZ (6 * 1056) uint8_t reserved[ROC_NIX_MEM_SZ] __plt_cache_aligned; } __plt_cache_aligned; From patchwork Fri Oct 14 05:43:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118188 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 88CE4A00C2; Fri, 14 Oct 2022 07:44:28 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 41CD642C56; Fri, 14 Oct 2022 07:43:53 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id B36B742C51 for ; Fri, 14 Oct 2022 07:43:51 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29E2JCgY005257 for ; Thu, 13 Oct 2022 22:43:50 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=HD5JQZM2rtAiWE38DPNWliOS5+nk2XVFGc0nZoQt1qg=; b=X3P1uRZSsxW6hC3HWqU3K0wJDz+QMtvTsk/JFRLJwPuYIVBqH10lKm933pxKnT0l9MRo IV7YzB1+IMaG+KX/tGjDptt1J98WhMJiPinPzDj5xzhgTUFay91+9L2Kb+17XiWElX/a YrIiUHMdcfu1AIMEy6eHiSjuqe6P06aSG7xv/We/l2OO7n1n1yxBYPt8VjIwUPKJ0Wgx iRyGz8dcJJULq99LikugSJ1Pke8fSrbVfK3PYkCOAc28dvNBBdc0Fym9PdpGreO67XOy 6lLyRWlfe1zwAuKezVPcq8lKdjGAUTn6hcqyfLKx6WSh1h+Ph6LaAHbA7XLfymWru4ij oQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3k6xvp0k7m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 13 Oct 2022 22:43:50 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 13 Oct 2022 22:43:49 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 13 Oct 2022 22:43:49 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 3AE5A3F7071; Thu, 13 Oct 2022 22:43:45 -0700 (PDT) From: Nithin Dabilpuram To: Pavan Nikhilesh , Shijith Thotton , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , , Vidya Sagar Velumuri Subject: [PATCH v3 11/13] net/cnxk: remove unnecessary dptr update Date: Fri, 14 Oct 2022 11:13:15 +0530 Message-ID: <20221014054317.1151306-11-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014054317.1151306-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221014054317.1151306-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: N0DvKfEeSwTOiM6fuEfEDmaVPyAjXepJ X-Proofpoint-GUID: N0DvKfEeSwTOiM6fuEfEDmaVPyAjXepJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_02,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Also remove ESN update from ucode command word 0 based on latest ucode. Signed-off-by: Nithin Dabilpuram Signed-off-by: Vidya Sagar Velumuri --- drivers/event/cnxk/cn9k_worker.h | 1 - drivers/net/cnxk/cn10k_tx.h | 4 ---- 2 files changed, 5 deletions(-) diff --git a/drivers/event/cnxk/cn9k_worker.h b/drivers/event/cnxk/cn9k_worker.h index 881861f348..4c3932da47 100644 --- a/drivers/event/cnxk/cn9k_worker.h +++ b/drivers/event/cnxk/cn9k_worker.h @@ -718,7 +718,6 @@ cn9k_sso_hws_xmit_sec_one(const struct cn9k_eth_txq *txq, uint64_t base, esn = outb_priv->esn; outb_priv->esn = esn + 1; - ucode_cmd[0] |= (esn >> 32) << 16; esn_lo = rte_cpu_to_be_32(esn & (BIT_ULL(32) - 1)); esn_hi = rte_cpu_to_be_32(esn >> 32); diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index d375183f90..815cd2ff1f 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -422,8 +422,6 @@ cn10k_nix_prep_sec_vec(struct rte_mbuf *m, uint64x2_t *cmd0, uint64x2_t *cmd1, CNXK_ETHDEV_SEC_OUTB_EV_SUB << 20), cmd23, 0); cmd23 = vsetq_lane_u64((uintptr_t)m | 1, cmd23, 1); - dptr += l2_len; - /* Move to our line */ laddr = LMT_OFF(lbase, *lnum, *loff ? 64 : 0); @@ -564,8 +562,6 @@ cn10k_nix_prep_sec(struct rte_mbuf *m, uint64_t *cmd, uintptr_t *nixtx_addr, CNXK_ETHDEV_SEC_OUTB_EV_SUB << 20), cmd23, 0); cmd23 = vsetq_lane_u64((uintptr_t)m | 1, cmd23, 1); - dptr += l2_len; - /* Move to our line */ laddr = LMT_OFF(lbase, *lnum, *loff ? 64 : 0); From patchwork Fri Oct 14 05:43:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118189 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 14428A00C2; Fri, 14 Oct 2022 07:44:34 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5A89942C57; Fri, 14 Oct 2022 07:43:55 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 5E28542C5C for ; Fri, 14 Oct 2022 07:43:54 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29DJMNMh010235 for ; Thu, 13 Oct 2022 22:43:53 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=rS1WBoQh4isp7oDK3l/h2z+KgJed4miJKo6O5H3o9K4=; b=XbpF2xLXFaHRoRYrK01a3Pbwl/rvRrSWDU7luULyzJgPAvp3g/OV+n0NNV6U1sFp/ws2 jzrXF9qb2x75ejUpl40HoSVx+3Vj0f9iOV4//UjQnQXnzYUk/5TBrCaeoz7cJ1B8SEhp mUL8pS3Wju07zu7oI2/rOX+XAD1H3Pf6ta10yCdL3JluPHR+evAJ7AsZVm+hkwj9YNmX FhrRKPU3t1+hrkwEonrtl23nkv99XoLIXK3qMyBrqcRCyshDEJA4t7S8mGw/RsQfYRmL FXSb4I0r3FS4y6ePw4iea3+2fkbXtQlZno6re0WTVDJYMAzYifpFq+m2+3qS+4gEESQl MQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k6fwvcbgm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 13 Oct 2022 22:43:53 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 13 Oct 2022 22:43:51 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Thu, 13 Oct 2022 22:43:51 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 855483F7048; Thu, 13 Oct 2022 22:43:49 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v3 12/13] net/cnxk: remove duplicate mempool debug checks Date: Fri, 14 Oct 2022 11:13:16 +0530 Message-ID: <20221014054317.1151306-12-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014054317.1151306-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221014054317.1151306-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: dRD9ICuxjJR3f8E3ikcTWi9pMzV0p92U X-Proofpoint-ORIG-GUID: dRD9ICuxjJR3f8E3ikcTWi9pMzV0p92U X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_01,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Remove duplicate mempool debug checks for mbufs received. Fixes: 592642c494b1 ("net/cnxk: align prefetches to CN10K cache model") Signed-off-by: Nithin Dabilpuram --- drivers/net/cnxk/cn10k_rx.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/net/cnxk/cn10k_rx.h b/drivers/net/cnxk/cn10k_rx.h index cf390a0361..4e22ceda02 100644 --- a/drivers/net/cnxk/cn10k_rx.h +++ b/drivers/net/cnxk/cn10k_rx.h @@ -1307,12 +1307,6 @@ cn10k_nix_recv_pkts_vector(void *args, struct rte_mbuf **mbufs, uint16_t pkts, ol_flags3 |= nix_rx_olflags_get(lookup_mem, cq3_w1); } - /* Mark mempool obj as "get" as it is alloc'ed by NIX */ - RTE_MEMPOOL_CHECK_COOKIES(mbuf0->pool, (void **)&mbuf0, 1, 1); - RTE_MEMPOOL_CHECK_COOKIES(mbuf1->pool, (void **)&mbuf1, 1, 1); - RTE_MEMPOOL_CHECK_COOKIES(mbuf2->pool, (void **)&mbuf2, 1, 1); - RTE_MEMPOOL_CHECK_COOKIES(mbuf3->pool, (void **)&mbuf3, 1, 1); - /* Translate meta to mbuf */ if (flags & NIX_RX_OFFLOAD_SECURITY_F) { uint64_t cq0_w5 = *CQE_PTR_OFF(cq0, 0, 40, flags); From patchwork Fri Oct 14 05:43:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nithin Dabilpuram X-Patchwork-Id: 118190 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1F079A00C2; Fri, 14 Oct 2022 07:44:39 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5C20342C5F; Fri, 14 Oct 2022 07:43:58 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id DEF0842C51 for ; Fri, 14 Oct 2022 07:43:56 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29E2JCPk005248 for ; Thu, 13 Oct 2022 22:43:56 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=kFUCEUdvgll99Is+D6hKtdWs7HOT0zty9yqEyVe8oBs=; b=UmDP0WB7wzSZ8v4CCLJRY+D8lITtNTk+jhJcRAlNg3uRVCAmsoUfzNJ/y/d0YFglTr8Z 1f1THGB1odixqY+D8MNBRc9yB0JAOFykZd9JQYWy1S3vP0vwhJbkGEuoUAl2WZfFVusv 0+malMCqTFVo3iTqwDd244ShgWpGmH0EVQ1mPoz1KBKeLd513gWc7Wjf20wyZHnypiE8 XyD2MCvWipt7xbF4rGldPSh25SNr99svdyDBHXQq+UnlDOw7+uVhjMW8e46rwLORqGVk ZMr46DXwojIIR8X3T6j9dCqBP6QMkmjoWgMbK0m5Ra3hz0m6PUQ2CKhsPD7iLWfFfmaC TQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3k6xvp0k7w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 13 Oct 2022 22:43:56 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 13 Oct 2022 22:43:54 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 13 Oct 2022 22:43:54 -0700 Received: from localhost.localdomain (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 186063F7058; Thu, 13 Oct 2022 22:43:51 -0700 (PDT) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , Vamsi Attunuru Subject: [PATCH v3 13/13] net/cnxk: handle hard expiry events Date: Fri, 14 Oct 2022 11:13:17 +0530 Message-ID: <20221014054317.1151306-13-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014054317.1151306-1-ndabilpuram@marvell.com> References: <20221011120135.45846-1-ndabilpuram@marvell.com> <20221014054317.1151306-1-ndabilpuram@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ExFr6gxCLfY2iXk4LEqfOskW7fcF5lU_ X-Proofpoint-GUID: ExFr6gxCLfY2iXk4LEqfOskW7fcF5lU_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-14_02,2022-10-13_01,2022-06-22_01 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vamsi Attunuru Based on the hard limits configured in the SA context, PMD passes corresponding event subtype to the application to notify hard expiry event Signed-off-by: Vamsi Attunuru --- drivers/net/cnxk/cn10k_ethdev_sec.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c index ce1b10d885..ed5c335787 100644 --- a/drivers/net/cnxk/cn10k_ethdev_sec.c +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c @@ -479,6 +479,12 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args, uint32_t soft_exp_event) case ROC_IE_OT_UCC_ERR_SA_OVERFLOW: desc.subtype = RTE_ETH_EVENT_IPSEC_ESN_OVERFLOW; break; + case ROC_IE_OT_UCC_ERR_SA_EXPIRED: + if (sa->w2.s.life_unit == ROC_IE_OT_SA_LIFE_UNIT_PKTS) + desc.subtype = RTE_ETH_EVENT_IPSEC_SA_PKT_HARD_EXPIRY; + else + desc.subtype = RTE_ETH_EVENT_IPSEC_SA_BYTE_HARD_EXPIRY; + break; case ROC_IE_OT_UCC_ERR_PKT_IP: warn_cnt++; if (warn_cnt % 10000 == 0)