From patchwork Tue Feb 14 12:57:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: rongwei liu X-Patchwork-Id: 123888 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DEEF741C49; Tue, 14 Feb 2023 13:57:43 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CD66242D62; Tue, 14 Feb 2023 13:57:43 +0100 (CET) Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2048.outbound.protection.outlook.com [40.107.96.48]) by mails.dpdk.org (Postfix) with ESMTP id B683742D62 for ; Tue, 14 Feb 2023 13:57:39 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=EWQMxfhmAnxBdwGbcS5/M+OxKUdGzK5kNeWLWS7ARJn1reXakIA51ikT2jH/jePYE3Cl+a3Xoctg9ARkydlbXR23T8lNZsr2f5MhfFLDjSYEpJI4tTqkE7od2onXKXlIAflXYgW3U0ny2kW8TmdWlOpi3Lh6ifrCY/f092Ax5zbu+qUFxnVGzV5mKgtKD+jJOBuCNCp4uxj93SA/gWFNnZbiAH/ctINpfmiiGfSrk73/D7BMoBTUtmN41mq7M76dmsJGTgCgb5PWjca0LC0GuQsokMVPZr9cmNQwZALiBjETHczonZkYdkHQ6MS+EOyNr9iBU8P9o3tB6gto7/Pdqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vC4v1JPJbilX0hZs5V94dpkmFkpnBte1S4wAwaFDwPw=; b=KGjNoABrRHANoOdATGONPW3e7N9aAdMj1C3KYeuCJaFAnWMFHE3SbJyOE9cw3CoiCYSpMM3O7YdfH913vUyj1zyBgHbVLAkfJNFtlt1jxXQVcEo5ZKNzr0B+nwwIS9qyUGKfPBLoS3NwGtuB083MvKp07+edWF3o8BowMU7WkSFNR8F7li/cN3o5joWSQYvvBETAgdrUmmUHXtS3SrsUT/GJ5JIOc0W4a55FMwgxn/rbBK/UE2YRQQ2NN0+OsUCRSf7WsAN7UbEaEh1DQ6TUalMNtS+OuV9TGRaTxBaH3+7DaeLISzPjnsCvmn6Zhz+1eLByq5BuqZD/uaJrf1ljog== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vC4v1JPJbilX0hZs5V94dpkmFkpnBte1S4wAwaFDwPw=; b=F80O+w7UEzaq+voIsW65QoN4LDl2FsFowRS0KOri6HucrXX0j/rPLAl2fuIo3rD+nT1vcA6Y8JsITng+P463LZ/ibsncXoNCAAOsjSZW7PHKhWPh2VVb0NtR0S+HfgU08AtcPWK3uHKn6JQmM1GSErSImbHbYJfKDHi/miNz+zuhgXEfILOL4fqbGyereES2etKpNspgJ8igVGlNSvaXzlKwcBg/bD5bjEuTBW1BX1HUFPhtIKWnmV5FgTgoPqxAbM72W61iQraO92QAy52XYTMXEASbJtuu149efuZDFAZjgGEUMsR1qPR16Pnslgi3QpQaWstg1NgVxmIYmd55hg== Received: from DM6PR02CA0118.namprd02.prod.outlook.com (2603:10b6:5:1b4::20) by MW3PR12MB4410.namprd12.prod.outlook.com (2603:10b6:303:5b::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.24; Tue, 14 Feb 2023 12:57:37 +0000 Received: from DM6NAM11FT074.eop-nam11.prod.protection.outlook.com (2603:10b6:5:1b4:cafe::52) by DM6PR02CA0118.outlook.office365.com (2603:10b6:5:1b4::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.24 via Frontend Transport; Tue, 14 Feb 2023 12:57:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT074.mail.protection.outlook.com (10.13.173.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.26 via Frontend Transport; Tue, 14 Feb 2023 12:57:37 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 14 Feb 2023 04:57:29 -0800 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 14 Feb 2023 04:57:26 -0800 From: Rongwei Liu To: , , , , CC: Subject: [PATCH v3 1/5] net/mlx5: adopt IPv6 routing extension prm definition Date: Tue, 14 Feb 2023 14:57:07 +0200 Message-ID: <20230214125711.3791966-2-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230214125711.3791966-1-rongweil@nvidia.com> References: <20230213113747.3677487-2-rongweil@nvidia.com> <20230214125711.3791966-1-rongweil@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT074:EE_|MW3PR12MB4410:EE_ X-MS-Office365-Filtering-Correlation-Id: ac0669bd-44a3-471b-dab6-08db0e8b0c69 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +Aspl3Xjb1nkQvbsvlVio7NureLspGz85+GycXryJWmhxXg64vTxH+oRo/sqdV9g51BV1L/gKt8ezIGuyoG8+1BJwPzg7hfolbci2Qqs71aMlk+tcHdMYsnPVp0W5eFA2jLN3mz4Hup6dVmZD7VYXUVu/uWy9iy8w7eF8pmHwwdwz7DM53Sju0zCM//aBCTKoxBIZLCVpY/sLpggUOiXxVQPxYbVFCDhdml9ZbAVDJxFSHJx87/r5lg3qKRROmkKoFP2+qwv2mkcdO2b/hGoJW/lZ3G92M9gs12vuaTfuHc+peIS0EspPRWN7vPG/YzzVwOUsW8eXc1o/gE9mQRaP4bqGkdQwecCWRfPotO3NkOekKMlQ4IumfWJGfUTjOoFDXXEsRuBlks8xseBcU0RwSaWNFEON+ATA6YwZT6qcfIQZVhgqyw8cLW3z6B9AyilMMDC+0bSj0BqSbH2lGT9TJkKwrXcJPpa+kkoIhXuBudetpAaOYX/lglh6san99rFMutsTvFfxuu+0NFXC3ZAiTqhGh0qT0OHtkm6nXwEz5Ke0XyutDD6t2ltLF9ymg2npNo3nqeP9HdorU3kaG9+IgOQ12X9IAAmJQY/aoCsU8MrLZ39FkzoBu/tSZ74H1DbOPb/z+dmMERkzxaanerJqSrol5cAtWqZL8irjmbmIraG8I4PTkSh67yzG8Anwn3zUBLcTXqLxfPsBbSb1Cw3kQ== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(396003)(136003)(346002)(376002)(39860400002)(451199018)(46966006)(36840700001)(40470700004)(47076005)(40460700003)(16526019)(186003)(6286002)(26005)(36756003)(1076003)(6666004)(83380400001)(2616005)(82310400005)(426003)(107886003)(4326008)(8936002)(5660300002)(70206006)(8676002)(70586007)(2906002)(336012)(41300700001)(55016003)(478600001)(7696005)(40480700001)(110136005)(316002)(36860700001)(82740400003)(356005)(7636003)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2023 12:57:37.3001 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac0669bd-44a3-471b-dab6-08db0e8b0c69 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT074.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4410 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Per newest PRM definition, sample_id stands for 3 parts of information instead of single uint32_t id: sample_id + modify_filed_id + format_select_dw. Also new FW capability bits have been introduces to identify the new capability. Signed-off-by: Rongwei Liu Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 14 +++++++++++--- drivers/common/mlx5/mlx5_devx_cmds.h | 7 ++++++- drivers/common/mlx5/mlx5_prm.h | 28 ++++++++++++++++++++++++++-- drivers/net/mlx5/mlx5.c | 15 +++++++++++---- drivers/net/mlx5/mlx5.h | 3 ++- drivers/net/mlx5/mlx5_flow_flex.c | 14 +++++++++++--- 6 files changed, 67 insertions(+), 14 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index e3a4927d0f..1f65ea7dcb 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -607,7 +607,8 @@ mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, - uint32_t ids[], uint32_t num) + struct mlx5_ext_sample_id ids[], + uint32_t num, uint8_t *anchor) { uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0}; @@ -636,6 +637,7 @@ mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, (void *)flex_obj); return -rte_errno; } + *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { void *s_off = (void *)((char *)sample + i * MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); @@ -645,8 +647,8 @@ mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, flow_match_sample_en); if (!en) continue; - ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off, - flow_match_sample_field_id); + ids[idx++].id = MLX5_GET(parse_graph_flow_match_sample, s_off, + flow_match_sample_field_id); } if (num != idx) { rte_errno = EINVAL; @@ -794,6 +796,12 @@ mlx5_devx_cmd_query_hca_parse_graph_node_cap max_num_arc_out); attr->max_num_sample = MLX5_GET(parse_graph_node_cap, hcattr, max_num_sample); + attr->anchor_en = MLX5_GET(parse_graph_node_cap, hcattr, anchor_en); + attr->ext_sample_id = MLX5_GET(parse_graph_node_cap, hcattr, ext_sample_id); + attr->sample_tunnel_inner2 = MLX5_GET(parse_graph_node_cap, hcattr, + sample_tunnel_inner2); + attr->zero_size_supported = MLX5_GET(parse_graph_node_cap, hcattr, + zero_size_supported); attr->sample_id_in_out = MLX5_GET(parse_graph_node_cap, hcattr, sample_id_in_out); attr->max_base_header_length = MLX5_GET(parse_graph_node_cap, hcattr, diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index c94b9eac06..5b33010155 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -114,6 +114,10 @@ struct mlx5_hca_flex_attr { uint8_t max_num_arc_out; uint8_t max_num_sample; uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */ + uint8_t anchor_en:1; + uint8_t ext_sample_id:1; + uint8_t sample_tunnel_inner2:1; + uint8_t zero_size_supported:1; uint8_t sample_id_in_out:1; uint16_t max_base_header_length; uint8_t max_sample_base_offset; @@ -706,7 +710,8 @@ int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir, struct mlx5_devx_modify_tir_attr *tir_attr); __rte_internal int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, - uint32_t ids[], uint32_t num); + struct mlx5_ext_sample_id ids[], + uint32_t num, uint8_t *anchor); __rte_internal struct mlx5_devx_obj * diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 243952bf85..d93b0bfbae 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1895,7 +1895,11 @@ struct mlx5_ifc_parse_graph_node_cap_bits { u8 max_num_arc_in[0x08]; u8 max_num_arc_out[0x08]; u8 max_num_sample[0x08]; - u8 reserved_at_78[0x07]; + u8 reserved_at_78[0x03]; + u8 anchor_en[0x1]; + u8 ext_sample_id[0x1]; + u8 sample_tunnel_inner2[0x1]; + u8 zero_size_supported[0x1]; u8 sample_id_in_out[0x1]; u8 max_base_header_length[0x10]; u8 reserved_at_90[0x08]; @@ -1905,6 +1909,24 @@ struct mlx5_ifc_parse_graph_node_cap_bits { u8 header_length_mask_width[0x08]; }; +/* ext_sample_id structure, see PRM Table: Flow Match Sample ID Format. */ +struct mlx5_ext_sample_id { + union { + struct { +#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN + uint32_t format_select_dw:8; + uint32_t modify_field_id:12; + uint32_t sample_id:12; +#else + uint32_t sample_id:12; + uint32_t modify_field_id:12; + uint32_t format_select_dw:8; +#endif + }; + uint32_t id; + }; +}; + struct mlx5_ifc_flow_table_prop_layout_bits { u8 ft_support[0x1]; u8 flow_tag[0x1]; @@ -4577,7 +4599,9 @@ struct mlx5_ifc_parse_graph_flex_bits { u8 header_length_mode[0x4]; u8 header_length_field_offset[0x10]; u8 next_header_field_offset[0x10]; - u8 reserved_at_160[0x1b]; + u8 reserved_at_160[0x12]; + u8 head_anchor_id[0x6]; + u8 reserved_at_178[0x3]; u8 next_header_field_size[0x5]; u8 header_length_field_mask[0x20]; u8 reserved_at_224[0x20]; diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index b8643cebdd..0b97c4e78d 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -964,11 +964,13 @@ int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) { struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex; struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; struct mlx5_devx_graph_node_attr node = { .modify_field_select = 0, }; - uint32_t ids[8]; + struct mlx5_ext_sample_id ids[8]; + uint8_t anchor_id; int ret; if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) { @@ -1004,15 +1006,20 @@ mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) return (rte_errno == 0) ? -ENODEV : -rte_errno; } prf->num = 2; - ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num); + ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num, &anchor_id); if (ret) { DRV_LOG(ERR, "Failed to query sample IDs."); return (rte_errno == 0) ? -ENODEV : -rte_errno; } prf->offset[0] = 0x0; prf->offset[1] = sizeof(uint32_t); - prf->ids[0] = ids[0]; - prf->ids[1] = ids[1]; + if (attr->ext_sample_id) { + prf->ids[0] = ids[0].sample_id; + prf->ids[1] = ids[1].sample_id; + } else { + prf->ids[0] = ids[0].id; + prf->ids[1] = ids[1].id; + } return 0; } diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 16b33e1548..83fb316ad8 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1307,9 +1307,10 @@ struct mlx5_lag { struct mlx5_flex_parser_devx { struct mlx5_list_entry entry; /* List element at the beginning. */ uint32_t num_samples; + uint8_t anchor_id; void *devx_obj; struct mlx5_devx_graph_node_attr devx_conf; - uint32_t sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; + struct mlx5_ext_sample_id sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; }; /* Pattern field descriptor - how to translate flex pattern into samples. */ diff --git a/drivers/net/mlx5/mlx5_flow_flex.c b/drivers/net/mlx5/mlx5_flow_flex.c index fb08910ddb..35f2a9923d 100644 --- a/drivers/net/mlx5/mlx5_flow_flex.c +++ b/drivers/net/mlx5/mlx5_flow_flex.c @@ -226,15 +226,18 @@ mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_4); void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4); + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex; struct mlx5_flex_item *tp; uint32_t i, pos = 0; + uint32_t sample_id; RTE_SET_USED(dev); MLX5_ASSERT(item->spec && item->mask); spec = item->spec; mask = item->mask; tp = (struct mlx5_flex_item *)spec->handle; - MLX5_ASSERT(mlx5_flex_index(dev->data->dev_private, tp) >= 0); + MLX5_ASSERT(mlx5_flex_index(priv, tp) >= 0); for (i = 0; i < tp->mapnum; i++) { struct mlx5_flex_pattern_field *map = tp->map + i; uint32_t id = map->reg_id; @@ -257,9 +260,13 @@ mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, MLX5_ASSERT(id < num_samples); id += num_samples; } + if (attr->ext_sample_id) + sample_id = tp->devx_fp->sample_ids[id].sample_id; + else + sample_id = tp->devx_fp->sample_ids[id].id; mlx5_flex_set_match_sample(misc4_m, misc4_v, def, msk & def, val & msk & def, - tp->devx_fp->sample_ids[id], id); + sample_id, id); pos += map->width; } } @@ -1298,7 +1305,8 @@ mlx5_flex_parser_create_cb(void *list_ctx, void *ctx) /* Query the firmware assigned sample ids. */ ret = mlx5_devx_cmd_query_parse_samples(fp->devx_obj, fp->sample_ids, - fp->num_samples); + fp->num_samples, + &fp->anchor_id); if (ret) goto error; DRV_LOG(DEBUG, "DEVx flex parser %p created, samples num: %u", From patchwork Tue Feb 14 12:57:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: rongwei liu X-Patchwork-Id: 123889 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2996841C49; Tue, 14 Feb 2023 13:57:49 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0E0EF42D75; Tue, 14 Feb 2023 13:57:46 +0100 (CET) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2055.outbound.protection.outlook.com [40.107.93.55]) by mails.dpdk.org (Postfix) with ESMTP id 2C77642D75 for ; Tue, 14 Feb 2023 13:57:45 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VzSUT/9ZKHvwKsdED760mfVTcWzHyaal9rjj+90SfblgPAcVrzwAo4kHhqPnXcnfxgDEpdsoJvAkIQqMtQtSPCFmHcsa0Ezlg4QdM2IQk/Cvad5coR3sQEBHcFXWzsBIKRO4MzIMwjJPg/JwWsbuhfdtnID+tGc2bzTPODdUqh+OhLxEAlwbMMeejqD3NPeojxeyZbHOcSLZRsL7O1rxXrg9V4uaAx4Rf9AmIn/xubioXZJ613aAJ/o/Ybeaimmj0WcuuCLvSpnq5vq5epy0Un2Wd7ltAr4ogDBLL6aW4FUJpbzqux3txYWvNvmXPvzCB0Ai46nz4RieV8KgFKx8AQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=b+AZCkXaEhc4ajQHgdo/45U96eGVzcadNl4xSu/CC2w=; b=JPIHN8oHPFixAywgTyaMWlHnJmcxXRcE5/63cMzNcBhmOopzZfmjYCiRDUfFg+fC2FGElrLJXEnepF5XSviIB8tBgVI4OOZqFS6EsGNVhwXU5N6gpc2jUBJcVtTiiQwR+4WXHAGqAph7TSZHKvhFq7RvY9VfrCR9EyWH5Qu/vXr19A59x8fouhnTADSzV60WVy0LINYieZB0qrZT+jCUWnFBCU827rF7KzZoUw+g2JNQcjgkrfewwj9uKVpckCYO9zrQb27WLhMH/7AG8NyMMl7yuCSx2aaPciVAkoCxTjF3YGp/gcm9zj3MrCNW4z0DfPmYA1pTspVdiQzqx0zyvg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=b+AZCkXaEhc4ajQHgdo/45U96eGVzcadNl4xSu/CC2w=; b=cJobvm20TX2vYe7JNT02/VjSligEe3HA1Xcq2K+nMSV8aJue4DXGEuJvtP/W5BQcSlR8CARX3gpe+YSGhgw0cxT2JhiyewVEbbGuYU0Veu5MG8AZ1kXNUqW0rDc+XB1YRcrIi3p965kzF2HH6kQ3R6qoAyTRNtTB4m6VwlZLDragJNmdbALRxkbzs9s7KTnXU7+MQq6qKh3R2MZ9U5eXu0wDojK1MSHYUNjIw33RbM9NkjRrPkG5DD7e6XI7QYEbPZRukDHGaI9ZZwUm82tJEhy/7be1lVYRt/AbASx3EiKynbJI8g6b47RtZKrIqZJ7cCWVWrcZ8gtOzod7j/EEbQ== Received: from DM6PR08CA0041.namprd08.prod.outlook.com (2603:10b6:5:1e0::15) by CH3PR12MB8211.namprd12.prod.outlook.com (2603:10b6:610:125::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.24; Tue, 14 Feb 2023 12:57:43 +0000 Received: from DM6NAM11FT023.eop-nam11.prod.protection.outlook.com (2603:10b6:5:1e0:cafe::cf) by DM6PR08CA0041.outlook.office365.com (2603:10b6:5:1e0::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.24 via Frontend Transport; Tue, 14 Feb 2023 12:57:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT023.mail.protection.outlook.com (10.13.173.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.24 via Frontend Transport; Tue, 14 Feb 2023 12:57:43 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 14 Feb 2023 04:57:32 -0800 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 14 Feb 2023 04:57:29 -0800 From: Rongwei Liu To: , , , , CC: , Gregory Etelson , Alex Vesker Subject: [PATCH v3 2/5] net/mlx5/hws: Definer, add mlx5dr context to definer_conv_data Date: Tue, 14 Feb 2023 14:57:08 +0200 Message-ID: <20230214125711.3791966-3-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230214125711.3791966-1-rongweil@nvidia.com> References: <20230213113747.3677487-2-rongweil@nvidia.com> <20230214125711.3791966-1-rongweil@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT023:EE_|CH3PR12MB8211:EE_ X-MS-Office365-Filtering-Correlation-Id: c3183308-d189-46cf-9a1a-08db0e8b1011 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: NQ524aQxBEa5SL5b/B2FnwDGj2zy7rnyVSYKRLoXr+LFPWCN69u4zewd0KJPJCznnEieZ888hI7MueftcVyAb6A3CkotbegIuq38qLaBGAgYRJtleEvmVG0C/wZD7hxbJ3HXOcfReLOQMWrcH1JSf/Nb4i2gpdKIdxnbcZwWMNm3V/4pUSXIlaPcd4K/+cM723uVupKbhVjXswkW1TD0GE1QiuTcwAi7JuS8+eZ2zcmnsxfSHGwG+CJqstF5ONbTfh2AnPTcOYE5+9r1SqCUOejKnCQGsZYlId/JPIGYK5hAmW8qbU/sKprbuMfto225x/KAzj/fEUMJCsAbAD3Ga8//7GWy53C2IonTZViRNuuOIXZDx1AvrtLkW749uR6XWOjLxIg5igYPkPegzPuRDokhU+k2D57O/AxJMMM7B1xJ11IttnntnOlbd+QzgTn+OoIXLHxUwd6zBJJdudGeLHNNZxaLKlcWDkMhR3sxfvThQ5GWT75U0IIAANgbQGIx/Ax+CaFQlmVhkAdYvP0iTwUBWPe+lr4ifmbIrT+pU8+KQi3880JCg65XNgziB2wR1D86Yc4QYVay6ERckYbv4b5QKwHRSahDIaJ7RVW87f+VrtQHmSFL1asa7pSjQp5BEHaJD8YRqwKMBBpsLiRODsODHMbFwVH6brDenMui5stbFQb+MkMC43ZSw4VeDcBnSApsmgs8YP+dyRDcybIsX0P6K1xkvw3b6pwqDHBE+c5ScjRaXPxRXLJDNnZ8/ocj X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(376002)(346002)(39860400002)(136003)(396003)(451199018)(36840700001)(40470700004)(46966006)(86362001)(6286002)(40460700003)(16526019)(26005)(82740400003)(356005)(186003)(6666004)(107886003)(1076003)(2906002)(83380400001)(7636003)(36756003)(2616005)(336012)(82310400005)(55016003)(40480700001)(5660300002)(316002)(8936002)(7696005)(36860700001)(70586007)(4326008)(70206006)(47076005)(426003)(8676002)(478600001)(54906003)(41300700001)(110136005)(42413004)(32563001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2023 12:57:43.4483 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c3183308-d189-46cf-9a1a-08db0e8b1011 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8211 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Gregory Etelson New mlx5dr_context member replaces mlx5dr_cmd_query_caps. Capabilities structure is a member of mlx5dr_context. Signed-off-by: Gregory Etelson Signed-off-by: Rongwei Liu Reviewed-by: Alex Vesker Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/hws/mlx5dr_definer.c | 41 ++++++++++++++------------- 1 file changed, 22 insertions(+), 19 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index cb7e6011a0..dea460137d 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -100,7 +100,7 @@ struct mlx5dr_definer_sel_ctrl { }; struct mlx5dr_definer_conv_data { - struct mlx5dr_cmd_query_caps *caps; + struct mlx5dr_context *ctx; struct mlx5dr_definer_fc *fc; uint8_t relaxed; uint8_t tunnel; @@ -904,6 +904,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, int item_idx) { + struct mlx5dr_cmd_query_caps *caps = cd->ctx->caps; const struct rte_flow_item_gtp *m = item->mask; struct mlx5dr_definer_fc *fc; @@ -925,7 +926,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, } if (m->hdr.teid) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_TEID_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_TEID_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -933,11 +934,11 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, fc->item_idx = item_idx; fc->tag_set = &mlx5dr_definer_gtp_teid_set; fc->bit_mask = __mlx5_mask(header_gtp, teid); - fc->byte_off = cd->caps->format_select_gtpu_dw_1 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_1 * DW_SIZE; } if (m->hdr.gtp_hdr_info) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -946,12 +947,12 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_ext_flag_set; fc->bit_mask = __mlx5_mask(header_gtp, ext_hdr_flag); fc->bit_off = __mlx5_dw_bit_off(header_gtp, ext_hdr_flag); - fc->byte_off = cd->caps->format_select_gtpu_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_0 * DW_SIZE; } if (m->hdr.msg_type) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -960,7 +961,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_msg_type_set; fc->bit_mask = __mlx5_mask(header_gtp, msg_type); fc->bit_off = __mlx5_dw_bit_off(header_gtp, msg_type); - fc->byte_off = cd->caps->format_select_gtpu_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_0 * DW_SIZE; } return 0; @@ -971,12 +972,13 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, int item_idx) { + struct mlx5dr_cmd_query_caps *caps = cd->ctx->caps; const struct rte_flow_item_gtp_psc *m = item->mask; struct mlx5dr_definer_fc *fc; /* Overwrite GTP extension flag to be 1 */ if (!cd->relaxed) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -985,12 +987,12 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_ones_set; fc->bit_mask = __mlx5_mask(header_gtp, ext_hdr_flag); fc->bit_off = __mlx5_dw_bit_off(header_gtp, ext_hdr_flag); - fc->byte_off = cd->caps->format_select_gtpu_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_0 * DW_SIZE; } /* Overwrite next extension header type */ if (!cd->relaxed) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_2_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_DW_2_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -1000,14 +1002,14 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_mask_set = &mlx5dr_definer_ones_set; fc->bit_mask = __mlx5_mask(header_opt_gtp, next_ext_hdr_type); fc->bit_off = __mlx5_dw_bit_off(header_opt_gtp, next_ext_hdr_type); - fc->byte_off = cd->caps->format_select_gtpu_dw_2 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_dw_2 * DW_SIZE; } if (!m) return 0; if (m->hdr.type) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -1016,11 +1018,11 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_ext_hdr_pdu_set; fc->bit_mask = __mlx5_mask(header_gtp_psc, pdu_type); fc->bit_off = __mlx5_dw_bit_off(header_gtp_psc, pdu_type); - fc->byte_off = cd->caps->format_select_gtpu_ext_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_ext_dw_0 * DW_SIZE; } if (m->hdr.qfi) { - if (!(cd->caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { + if (!(caps->flex_protocols & MLX5_HCA_FLEX_GTPU_FIRST_EXT_DW_0_ENABLED)) { rte_errno = ENOTSUP; return rte_errno; } @@ -1029,7 +1031,7 @@ mlx5dr_definer_conv_item_gtp_psc(struct mlx5dr_definer_conv_data *cd, fc->tag_set = &mlx5dr_definer_gtp_ext_hdr_qfi_set; fc->bit_mask = __mlx5_mask(header_gtp_psc, qfi); fc->bit_off = __mlx5_dw_bit_off(header_gtp_psc, qfi); - fc->byte_off = cd->caps->format_select_gtpu_ext_dw_0 * DW_SIZE; + fc->byte_off = caps->format_select_gtpu_ext_dw_0 * DW_SIZE; } return 0; @@ -1040,18 +1042,19 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, int item_idx) { + struct mlx5dr_cmd_query_caps *caps = cd->ctx->caps; const struct rte_flow_item_ethdev *m = item->mask; struct mlx5dr_definer_fc *fc; uint8_t bit_offset = 0; if (m->port_id) { - if (!cd->caps->wire_regc_mask) { + if (!caps->wire_regc_mask) { DR_LOG(ERR, "Port ID item not supported, missing wire REGC mask"); rte_errno = ENOTSUP; return rte_errno; } - while (!(cd->caps->wire_regc_mask & (1 << bit_offset))) + while (!(caps->wire_regc_mask & (1 << bit_offset))) bit_offset++; fc = &cd->fc[MLX5DR_DEFINER_FNAME_VPORT_REG_C_0]; @@ -1060,7 +1063,7 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd, fc->tag_mask_set = &mlx5dr_definer_ones_set; DR_CALC_SET_HDR(fc, registers, register_c_0); fc->bit_off = bit_offset; - fc->bit_mask = cd->caps->wire_regc_mask >> bit_offset; + fc->bit_mask = caps->wire_regc_mask >> bit_offset; } else { DR_LOG(ERR, "Pord ID item mask must specify ID mask"); rte_errno = EINVAL; @@ -1673,7 +1676,7 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, int i, ret; cd.fc = fc; - cd.caps = ctx->caps; + cd.ctx = ctx; cd.relaxed = mt->flags & MLX5DR_MATCH_TEMPLATE_FLAG_RELAXED_MATCH; /* Collect all RTE fields to the field array and set header layout */ From patchwork Tue Feb 14 12:57:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: rongwei liu X-Patchwork-Id: 123891 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4155441C49; Tue, 14 Feb 2023 13:58:03 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8AFBC42DB8; Tue, 14 Feb 2023 13:57:51 +0100 (CET) Received: from NAM02-BN1-obe.outbound.protection.outlook.com (mail-bn1nam02on2042.outbound.protection.outlook.com [40.107.212.42]) by mails.dpdk.org (Postfix) with ESMTP id 2B7484067E for ; Tue, 14 Feb 2023 13:57:49 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=lrmLuQ6nYzKhceu6xIz/qlN8nu6fh49OJqH7c1eAkE2d1flVrDoNQ7aPzx5RSnbMko5GyQg1SK6fDkMq4o6jcWpCgpBFQId65N7IUB7lyi1jw2Ed8qySM+KVMCF4hrOaNcP03tkhpAZ7dyHHVIjRTJvXfkW/S+coGBu8Ts2kx3Ogiu1XKS/GrveEB4fWe/CsiF+z7CpQj9hxV5WPq0w/0wMFT+Gcerhs2Iygh0Hb92gYxD5VpxwCA8gRWBJftleQ/GxNKOU/frNp2yt+wIzboQ8R3Ng6TEx1AhvwwJdcXxHFYG0xFC/8YAD9iH+wp15zO65ch6iR8IPBWBWetszBiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=yTcqrmcMxVg2KO8by8IcznbPNvK4N7HHX20zByokwVU=; b=hlS+VVL6k7T1TSnnRdtodTVpkBu8dkN1cYoFfOf3TDRY4kLTgHp74PKvp6IDpf/vX70vi1qAwVULYRL5OcwXD3B/KmJG/+1+Iney9OOFqKrSk5uOzPUmJsMhrNq+6GUuNamUg8Pkfac2KWRVAjMkvDZJJFib4E46dQ1bHfgLaPACzXnUlYPTmpfN+IhaSk4+jzfe1UIz+2U2ahuaA+yPOrWK8rsjA9n3H1VHgq10w942tQHZxGz13h/oBT+kZrnTgW+/oggVGqvFOaI61zA+qg3O0E6jTGd3lY/+xUcgILGJvxNAh/BNp6H5a0kqDiKnHdpUvnIZrmyDtau/KLKrnw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yTcqrmcMxVg2KO8by8IcznbPNvK4N7HHX20zByokwVU=; b=f2TbU/PEieHjIeosdGHJVMo2OthDJTk9lviKroCxEXR7wbLdY879TKfhS+WZ/Q68KUiniwBIggaG0zrORhqUrU393m88bBWn4T+XBXLFoqwbvWxa0/F9WAjYma6YH/xf7Rng47CcrPLgJ5QT6+lNA0HhMY81u8t7MGPp3AxAuZWz/zyGiokFqWksUE7hf66V04ngdPhoQGARgR1b0EwrceIY2GkW5ShfaDKKQUo3w08YwT9qwtzvQgCl23mamWj0WxtjdDODxr+9+q0I/YF0ZvZZbHw0RCbcSnT4rCQsm2K+oWsXSBmn/IqTHK51FCEJZR9UeqL0gVqui6XDQU3S9Q== Received: from DM6PR08CA0047.namprd08.prod.outlook.com (2603:10b6:5:1e0::21) by DM4PR12MB5344.namprd12.prod.outlook.com (2603:10b6:5:39a::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.24; Tue, 14 Feb 2023 12:57:47 +0000 Received: from DM6NAM11FT023.eop-nam11.prod.protection.outlook.com (2603:10b6:5:1e0:cafe::fa) by DM6PR08CA0047.outlook.office365.com (2603:10b6:5:1e0::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.26 via Frontend Transport; Tue, 14 Feb 2023 12:57:47 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT023.mail.protection.outlook.com (10.13.173.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.24 via Frontend Transport; Tue, 14 Feb 2023 12:57:47 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 14 Feb 2023 04:57:34 -0800 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 14 Feb 2023 04:57:32 -0800 From: Rongwei Liu To: , , , , CC: , Alex Vesker Subject: [PATCH v3 3/5] net/mlx5/hws: add IPv6 routing extension matching support Date: Tue, 14 Feb 2023 14:57:09 +0200 Message-ID: <20230214125711.3791966-4-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230214125711.3791966-1-rongweil@nvidia.com> References: <20230213113747.3677487-2-rongweil@nvidia.com> <20230214125711.3791966-1-rongweil@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT023:EE_|DM4PR12MB5344:EE_ X-MS-Office365-Filtering-Correlation-Id: 7bd7807a-482f-4ac8-3bac-08db0e8b1244 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: n3+pLlkkS/HEDVwPoUZ7NU/EzKs4CG9X/5wLLygUkTlP2vydqavW9khq2hZ23ZZfbOBW0GHQdEghH0ZrFobbcjk7fvIHrgmHjZ7yNgaK10si8CENolG/wXx/QPNo748KqQ3zIhlYcK9/50jJQUNJ/fDNm5qc883ujPMZtHPuLsCEiP7xl7JwPSfZWXu1TinXNeBnDAfFt+G8eZJGQ2Sk/cD60ftOOr0FJTDQ2fSAWjJb61gViQZN0anlgmla2zMaLxkca2LWQxW+Sj1R6Js15DPkPODv4geA/TVAXCGtXqUE63e8ZqYj25N6GgEJdKFJM7msKb9nZ5NWTyhB+dmjxAafPMiHcxARy6l7AfQHi2/lmU7BR7DBZDdn/TsUX6hyQktwpSdIhsgBvcskDPKxO+TfxzQqxfQMpNTi+2BT/v/5pz2+bDIw0Ltfk/wV3ty8jHBubbyD69eAGmVRei/srb5Kt6iPFwkomX+0oZMRvSUzQm4sCi/dULPwbgEko5UEqd3EOF7fhtrpSLsIxDtPNST4KzBXcOAaEWehR8evAAUifhNGxEVlNuGoaF/ageW0ok/sdrZTwVCdJfUhbkjSYnnFP8C5+UFAomSWrWC1VywfkKxsf1zzpmBu1iknL3tC5dIMQwKDzdvSZGAH6JkW0PxNij5KgAtuaesIpdqDNQFd+G6dLIwiZGgceBkpDbUyIxLrOBhxCudIRIHgpqx1mg== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(136003)(376002)(39860400002)(396003)(346002)(451199018)(36840700001)(46966006)(40470700004)(54906003)(2906002)(30864003)(5660300002)(8936002)(41300700001)(70206006)(4326008)(70586007)(55016003)(8676002)(40480700001)(47076005)(316002)(110136005)(6666004)(1076003)(478600001)(7696005)(107886003)(186003)(26005)(36756003)(40460700003)(6286002)(16526019)(86362001)(83380400001)(82310400005)(2616005)(426003)(336012)(7636003)(82740400003)(356005)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2023 12:57:47.1199 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7bd7807a-482f-4ac8-3bac-08db0e8b1244 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5344 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add mlx5 HWS logic to match IPv6 routing extension header. Once detecting IPv6 matching extension items in pattern template create callback, PMD allocates a flex parser to sample the first dword of srv6 header. Only support next_hdr/segments_left/type for now. Signed-off-by: Rongwei Liu Reviewed-by: Alex Vesker Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 7 +- drivers/net/mlx5/hws/mlx5dr_definer.c | 91 ++++++++++++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_definer.h | 15 +++++ drivers/net/mlx5/mlx5.c | 92 ++++++++++++++++++++++++++- drivers/net/mlx5/mlx5.h | 16 +++++ drivers/net/mlx5/mlx5_flow.h | 28 ++++++++ drivers/net/mlx5/mlx5_flow_hw.c | 29 +++++++-- 7 files changed, 268 insertions(+), 10 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 1f65ea7dcb..22a94c1e1a 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -607,7 +607,7 @@ mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, - struct mlx5_ext_sample_id ids[], + struct mlx5_ext_sample_id *ids, uint32_t num, uint8_t *anchor) { uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0}; @@ -637,8 +637,9 @@ mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj, (void *)flex_obj); return -rte_errno; } - *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); - for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { + if (anchor) + *anchor = MLX5_GET(parse_graph_flex, flex, head_anchor_id); + for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM && idx <= num; i++) { void *s_off = (void *)((char *)sample + i * MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample)); uint32_t en; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index dea460137d..ce7cf0504d 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -125,6 +125,7 @@ struct mlx5dr_definer_conv_data { X(SET_BE16, ipv4_len, v->total_length, rte_ipv4_hdr) \ X(SET_BE16, ipv6_payload_len, v->hdr.payload_len, rte_flow_item_ipv6) \ X(SET, ipv6_proto, v->hdr.proto, rte_flow_item_ipv6) \ + X(SET, ipv6_routing_hdr, IPPROTO_ROUTING, rte_flow_item_ipv6) \ X(SET, ipv6_hop_limits, v->hdr.hop_limits, rte_flow_item_ipv6) \ X(SET_BE32P, ipv6_src_addr_127_96, &v->hdr.src_addr[0], rte_flow_item_ipv6) \ X(SET_BE32P, ipv6_src_addr_95_64, &v->hdr.src_addr[4], rte_flow_item_ipv6) \ @@ -293,6 +294,21 @@ mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc, DR_SET(tag, ok1_bits, fc->byte_off, fc->bit_off, fc->bit_mask); } +static void +mlx5dr_definer_ipv6_routing_ext_set(struct mlx5dr_definer_fc *fc, + const void *item, + uint8_t *tag) +{ + const struct rte_flow_item_ipv6_routing_ext *v = item; + uint32_t val; + + val = v->hdr.next_hdr << __mlx5_dw_bit_off(header_ipv6_routing_ext, next_hdr); + val |= v->hdr.type << __mlx5_dw_bit_off(header_ipv6_routing_ext, type); + val |= v->hdr.segments_left << + __mlx5_dw_bit_off(header_ipv6_routing_ext, segments_left); + DR_SET(tag, val, fc->byte_off, 0, fc->bit_mask); +} + static void mlx5dr_definer_gre_key_set(struct mlx5dr_definer_fc *fc, const void *item_spec, @@ -1605,6 +1621,76 @@ mlx5dr_definer_conv_item_meter_color(struct mlx5dr_definer_conv_data *cd, return 0; } +static struct mlx5dr_definer_fc * +mlx5dr_definer_get_flex_parser_fc(struct mlx5dr_definer_conv_data *cd, uint32_t byte_off) +{ + uint32_t byte_off_fp7 = MLX5_BYTE_OFF(definer_hl, flex_parser.flex_parser_7); + uint32_t byte_off_fp0 = MLX5_BYTE_OFF(definer_hl, flex_parser.flex_parser_0); + enum mlx5dr_definer_fname fname = MLX5DR_DEFINER_FNAME_FLEX_PARSER_0; + struct mlx5dr_definer_fc *fc; + uint32_t idx; + + if (byte_off < byte_off_fp7 || byte_off > byte_off_fp0) { + rte_errno = EINVAL; + return NULL; + } + idx = (byte_off_fp0 - byte_off) / (sizeof(uint32_t)); + fname += (enum mlx5dr_definer_fname)idx; + fc = &cd->fc[fname]; + fc->byte_off = byte_off; + fc->bit_mask = UINT32_MAX; + return fc; +} + +static int +mlx5dr_definer_conv_item_ipv6_routing_ext(struct mlx5dr_definer_conv_data *cd, + struct rte_flow_item *item, + int item_idx) +{ + const struct rte_flow_item_ipv6_routing_ext *m = item->mask; + struct mlx5dr_definer_fc *fc; + bool inner = cd->tunnel; + uint32_t byte_off; + + if (!cd->relaxed) { + fc = &cd->fc[DR_CALC_FNAME(IP_VERSION, inner)]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ipv6_version_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l2, l3_type, inner); + + /* Overwrite - Unset ethertype if present */ + memset(&cd->fc[DR_CALC_FNAME(ETH_TYPE, inner)], 0, sizeof(*fc)); + + fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)]; + if (!fc->tag_set) { + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ipv6_routing_hdr_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + DR_CALC_SET(fc, eth_l3, protocol_next_header, inner); + } + } + + if (!m) + return 0; + + if (m->hdr.hdr_len || m->hdr.flags) { + rte_errno = ENOTSUP; + return rte_errno; + } + + if (m->hdr.next_hdr || m->hdr.type || m->hdr.segments_left) { + byte_off = flow_hw_get_srh_flex_parser_byte_off_from_ctx(cd->ctx); + fc = mlx5dr_definer_get_flex_parser_fc(cd, byte_off); + if (!fc) + return rte_errno; + + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_ipv6_routing_ext_set; + } + return 0; +} + static int mlx5dr_definer_mt_set_fc(struct mlx5dr_match_template *mt, struct mlx5dr_definer_fc *fc, @@ -1786,6 +1872,11 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, ret = mlx5dr_definer_conv_item_meter_color(&cd, items, i); item_flags |= MLX5_FLOW_ITEM_METER_COLOR; break; + case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT: + ret = mlx5dr_definer_conv_item_ipv6_routing_ext(&cd, items, i); + item_flags |= cd.tunnel ? MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT : + MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT; + break; default: DR_LOG(ERR, "Unsupported item type %d", items->type); rte_errno = ENOTSUP; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index 464872acd6..7420971f4a 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -519,6 +519,21 @@ struct mlx5_ifc_header_ipv6_vtc_bits { u8 flow_label[0x14]; }; +struct mlx5_ifc_header_ipv6_routing_ext_bits { + u8 next_hdr[0x8]; + u8 hdr_len[0x8]; + u8 type[0x8]; + u8 segments_left[0x8]; + union { + u8 flags[0x20]; + struct { + u8 last_entry[0x8]; + u8 flag[0x8]; + u8 tag[0x10]; + }; + }; +}; + struct mlx5_ifc_header_vxlan_bits { u8 flags[0x8]; u8 reserved1[0x18]; diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 0b97c4e78d..94fd5a91e3 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -970,7 +970,6 @@ mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) .modify_field_select = 0, }; struct mlx5_ext_sample_id ids[8]; - uint8_t anchor_id; int ret; if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) { @@ -1006,7 +1005,7 @@ mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) return (rte_errno == 0) ? -ENODEV : -rte_errno; } prf->num = 2; - ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num, &anchor_id); + ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num, NULL); if (ret) { DRV_LOG(ERR, "Failed to query sample IDs."); return (rte_errno == 0) ? -ENODEV : -rte_errno; @@ -1041,6 +1040,95 @@ mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev) prf->obj = NULL; } +/* + * Allocation of a flex parser for srh. Once refcnt is zero, the resources held + * by this parser will be freed. + * @param dev + * Pointer to Ethernet device structure. + * + * @return + * 0 on success, a negative errno value otherwise and rte_errno is set. + */ +int +mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev) +{ + struct mlx5_devx_graph_node_attr node = { + .modify_field_select = 0, + }; + struct mlx5_ext_sample_id ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_common_dev_config *config = &priv->sh->cdev->config; + void *ibv_ctx = priv->sh->cdev->ctx; + int ret; + + memset(ids, 0xff, sizeof(ids)); + if (!config->hca_attr.parse_graph_flex_node) { + DRV_LOG(ERR, "Dynamic flex parser is not supported"); + return -ENOTSUP; + } + if (__atomic_add_fetch(&priv->sh->srh_flex_parser.refcnt, 1, __ATOMIC_RELAXED) > 1) + return 0; + + node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIELD; + /* Srv6 first two DW are not counted in. */ + node.header_length_base_value = 0x8; + /* The unit is uint64_t. */ + node.header_length_field_shift = 0x3; + /* Header length is the 2nd byte. */ + node.header_length_field_offset = 0x8; + node.header_length_field_mask = 0xF; + /* One byte next header protocol. */ + node.next_header_field_size = 0x8; + node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IP; + node.in[0].compare_condition_value = IPPROTO_ROUTING; + node.sample[0].flow_match_sample_en = 1; + /* First come first serve no matter inner or outer. */ + node.sample[0].flow_match_sample_tunnel_mode = MLX5_GRAPH_SAMPLE_TUNNEL_FIRST; + node.out[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_TCP; + node.out[0].compare_condition_value = IPPROTO_TCP; + node.out[1].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_UDP; + node.out[1].compare_condition_value = IPPROTO_UDP; + node.out[2].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IPV6; + node.out[2].compare_condition_value = IPPROTO_IPV6; + priv->sh->srh_flex_parser.fp = mlx5_devx_cmd_create_flex_parser(ibv_ctx, &node); + if (!priv->sh->srh_flex_parser.fp) { + DRV_LOG(ERR, "Failed to create flex parser node object."); + return (rte_errno == 0) ? -ENODEV : -rte_errno; + } + priv->sh->srh_flex_parser.num = 1; + ret = mlx5_devx_cmd_query_parse_samples(priv->sh->srh_flex_parser.fp, ids, + priv->sh->srh_flex_parser.num, + &priv->sh->srh_flex_parser.anchor_id); + if (ret) { + DRV_LOG(ERR, "Failed to query sample IDs."); + return (rte_errno == 0) ? -ENODEV : -rte_errno; + } + priv->sh->srh_flex_parser.offset[0] = 0x0; + priv->sh->srh_flex_parser.ids[0].id = ids[0].id; + return 0; +} + +/* + * Destroy the flex parser node, including the parser itself, input / output + * arcs and DW samples. Resources could be reused then. + * + * @param dev + * Pointer to Ethernet device structure + */ +void +mlx5_free_srh_flex_parser(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_internal_flex_parser_profile *fp = &priv->sh->srh_flex_parser; + + if (__atomic_sub_fetch(&fp->refcnt, 1, __ATOMIC_RELAXED)) + return; + if (fp->fp) + mlx5_devx_cmd_destroy(fp->fp); + fp->fp = NULL; + fp->num = 0; +} + uint32_t mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr) { diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 83fb316ad8..bea1f62ea8 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -543,6 +543,17 @@ struct mlx5_counter_stats_raw { volatile struct flow_counter_stats *data; }; +/* Mlx5 internal flex parser profile structure. */ +struct mlx5_internal_flex_parser_profile { + uint32_t num;/* Actual number of samples. */ + /* Sample IDs for this profile. */ + struct mlx5_ext_sample_id ids[MLX5_FLEX_ITEM_MAPPING_NUM]; + uint32_t offset[MLX5_FLEX_ITEM_MAPPING_NUM]; /* Each ID sample offset. */ + uint8_t anchor_id; + uint32_t refcnt; + void *fp; /* DevX flex parser object. */ +}; + TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); /* Counter global management structure. */ @@ -1436,6 +1447,7 @@ struct mlx5_dev_ctx_shared { struct mlx5_uar rx_uar; /* DevX UAR for Rx. */ struct mlx5_proc_priv *pppriv; /* Pointer to primary private process. */ struct mlx5_ecpri_parser_profile ecpri_parser; + struct mlx5_internal_flex_parser_profile srh_flex_parser; /* srh flex parser structure. */ /* Flex parser profiles information. */ LIST_HEAD(shared_rxqs, mlx5_rxq_ctrl) shared_rxqs; /* Shared RXQs. */ struct mlx5_aso_age_mng *aso_age_mng; @@ -2258,4 +2270,8 @@ struct mlx5_list_entry *mlx5_flex_parser_clone_cb(void *list_ctx, void *ctx); void mlx5_flex_parser_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry); + +int mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev); + +void mlx5_free_srh_flex_parser(struct rte_eth_dev *dev); #endif /* RTE_PMD_MLX5_H_ */ diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 86311b0b08..4bef2296b8 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -219,6 +219,10 @@ enum mlx5_feature_name { /* Meter color item */ #define MLX5_FLOW_ITEM_METER_COLOR (UINT64_C(1) << 44) +/* IPv6 routing extension item */ +#define MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT (UINT64_C(1) << 45) +#define MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT (UINT64_C(1) << 46) + /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) @@ -2615,4 +2619,28 @@ int mlx5_flow_item_field_width(struct rte_eth_dev *dev, enum rte_flow_field_id field, int inherit, const struct rte_flow_attr *attr, struct rte_flow_error *error); + +static __rte_always_inline int +flow_hw_get_srh_flex_parser_byte_off_from_ctx(void *dr_ctx __rte_unused) +{ +#ifdef HAVE_IBV_FLOW_DV_SUPPORT + uint16_t port; + + MLX5_ETH_FOREACH_DEV(port, NULL) { + struct mlx5_priv *priv; + struct mlx5_hca_flex_attr *attr; + + priv = rte_eth_devices[port].data->dev_private; + attr = &priv->sh->cdev->config.hca_attr.flex; + if (priv->dr_ctx == dr_ctx && attr->ext_sample_id) { + if (priv->sh->srh_flex_parser.num) + return priv->sh->srh_flex_parser.ids[0].format_select_dw * + sizeof(uint32_t); + else + return UINT32_MAX; + } + } +#endif + return UINT32_MAX; +} #endif /* RTE_PMD_MLX5_FLOW_H_ */ diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 798bcca710..6799b8a89f 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -213,17 +213,17 @@ flow_hw_hashfields_set(struct mlx5_flow_rss_desc *rss_desc, } /** - * Generate the pattern item flags. - * Will be used for shared RSS action. + * Generate the matching pattern item flags. * * @param[in] items * Pointer to the list of items. * * @return - * Item flags. + * Matching item flags. RSS hash field function + * silently ignores the flags which are unsupported. */ static uint64_t -flow_hw_rss_item_flags_get(const struct rte_flow_item items[]) +flow_hw_matching_item_flags_get(const struct rte_flow_item items[]) { uint64_t item_flags = 0; uint64_t last_item = 0; @@ -249,6 +249,10 @@ flow_hw_rss_item_flags_get(const struct rte_flow_item items[]) last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP : MLX5_FLOW_LAYER_OUTER_L4_UDP; break; + case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT: + last_item = tunnel ? MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT : + MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT; + break; case RTE_FLOW_ITEM_TYPE_GRE: last_item = MLX5_FLOW_LAYER_GRE; break; @@ -4738,6 +4742,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST: case RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REPLY: case RTE_FLOW_ITEM_TYPE_CONNTRACK: + case RTE_FLOW_ITEM_TYPE_IPV6_ROUTING_EXT: break; case RTE_FLOW_ITEM_TYPE_INTEGRITY: /* @@ -4866,7 +4871,7 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev, "cannot create match template"); return NULL; } - it->item_flags = flow_hw_rss_item_flags_get(tmpl_items); + it->item_flags = flow_hw_matching_item_flags_get(tmpl_items); if (copied_items) { if (attr->ingress) it->implicit_port = true; @@ -4874,6 +4879,17 @@ flow_hw_pattern_template_create(struct rte_eth_dev *dev, it->implicit_tag = true; mlx5_free(copied_items); } + /* Either inner or outer, can't both. */ + if (it->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT | + MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) { + if (((it->item_flags & MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT) && + (it->item_flags & MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) || + (mlx5_alloc_srh_flex_parser(dev))) { + claim_zero(mlx5dr_match_template_destroy(it->mt)); + mlx5_free(it); + return NULL; + } + } __atomic_fetch_add(&it->refcnt, 1, __ATOMIC_RELAXED); LIST_INSERT_HEAD(&priv->flow_hw_itt, it, next); return it; @@ -4905,6 +4921,9 @@ flow_hw_pattern_template_destroy(struct rte_eth_dev *dev __rte_unused, NULL, "item template in using"); } + if (template->item_flags & (MLX5_FLOW_ITEM_OUTER_IPV6_ROUTING_EXT | + MLX5_FLOW_ITEM_INNER_IPV6_ROUTING_EXT)) + mlx5_free_srh_flex_parser(dev); LIST_REMOVE(template, next); claim_zero(mlx5dr_match_template_destroy(template->mt)); mlx5_free(template); From patchwork Tue Feb 14 12:57:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: rongwei liu X-Patchwork-Id: 123890 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4C14441C49; Tue, 14 Feb 2023 13:57:57 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6A99842DAB; Tue, 14 Feb 2023 13:57:50 +0100 (CET) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2059.outbound.protection.outlook.com [40.107.220.59]) by mails.dpdk.org (Postfix) with ESMTP id E02A242D8B for ; Tue, 14 Feb 2023 13:57:48 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=U8ZmVAkbyFUtN/EoXQVEoXDZWoiwqRC1b6z46Cg7Vl4z9WSwbAsExCmA6rgX9g2fsn0xJ9m8Pw49W3bR8EB9NLOfXOpPqbo4ooB65ety6lGi4dDzERGOxbCZNDiUTZgdShiBhrBpd+b729yFmy04/YfZ5zQisvQV8U81zQhEtQg+7N+dhL8KRhVOdLn35sZFBvxHeSqe76Tfs5u8EaI5tTcVn1cXMWV4CcuXT+QxU2DWrggYblMgcDkIIdi1QNQkmqm1m4Ezmzma+7/3Af9J6A9KiiMa2lXIRydf88HDCpCbuborwq5SkS22yBW0a+qZunMNSTyjvs8NkH5o7Bvjnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=tJ9DmnOkcI98H3n+kr9ZDpsYcjQkcz9m0HFD8ETY+2Y=; b=j//QXcqRa4zk44O0w+DxloFnqLPwjAR69RBp6VY4d/+OzzOjLvcXZ/yA1A7zkQvQ7bJj4be4THJWoyO/ga8BxhSZuihJ0qX3eZVHe7aq5hG5Pp/mXY402y5RF0sKa6iCvNKBrDEKKDzTEu9mPLk0AH9+hpAtkvqroDe0E3pw0zgQWfF5egJ53/Z0C8kpUfBcYygDsmzjrixnMFadVGYJZfch25tHHJJLic12yZ7YEJ/9n4sGidtI6rXeroa5/9OXgkV2nHG9JmbySUZp25VyCDwwbbGeDt6vl0qORB4uyAy45+4YOxS5XdY+mc6kHlGdlZ+8Y9PGNeIfX5cxnoc6jg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tJ9DmnOkcI98H3n+kr9ZDpsYcjQkcz9m0HFD8ETY+2Y=; b=j74AbM1dSvUga4Lh0lMQsZ+ZiJXKoA5hwgRSvKmSy3YO9PwpUVaaPrE7Z0xsf3cgzJ7g7dEHP57OclGvLYHeYx0wnkJQjbTRaAABTnaR748jRZ+h2L5giCE9RuSo/Hlo/VdWtrtY9N5AKiA3uHno+N7K+9kw0ObiS6DMnDVGY+DOzblJERBB9BLo2ukx6cqtEEE+HmvE/e4TMv8S9ABrY75W+ZnunjXJT7t223hloMGf2s+n53umN9KDQrMeFsHZmOPmsk3gqzeTIIoNWyrKWBRXHUZwQ1QiysHJkeAU0IwwMG9Pfv2QM9nQWfiAGzFpw+BExfmE3kO0txIO+4YS5Q== Received: from BN9PR03CA0906.namprd03.prod.outlook.com (2603:10b6:408:107::11) by PH7PR12MB7968.namprd12.prod.outlook.com (2603:10b6:510:272::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.24; Tue, 14 Feb 2023 12:57:47 +0000 Received: from BN8NAM11FT069.eop-nam11.prod.protection.outlook.com (2603:10b6:408:107:cafe::9c) by BN9PR03CA0906.outlook.office365.com (2603:10b6:408:107::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.24 via Frontend Transport; Tue, 14 Feb 2023 12:57:47 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT069.mail.protection.outlook.com (10.13.176.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.24 via Frontend Transport; Tue, 14 Feb 2023 12:57:47 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 14 Feb 2023 04:57:37 -0800 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 14 Feb 2023 04:57:35 -0800 From: Rongwei Liu To: , , , , CC: Subject: [PATCH v3 4/5] net/mlx5/hws: add modify IPv6 protocol implementation Date: Tue, 14 Feb 2023 14:57:10 +0200 Message-ID: <20230214125711.3791966-5-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230214125711.3791966-1-rongweil@nvidia.com> References: <20230213113747.3677487-2-rongweil@nvidia.com> <20230214125711.3791966-1-rongweil@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT069:EE_|PH7PR12MB7968:EE_ X-MS-Office365-Filtering-Correlation-Id: f815fefa-c3b9-4f52-8982-08db0e8b123d X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: rybX7wAj3UnvyCvih59ho8Zw85mvgwRzd7Hd4GTMGvelXtm3aytaaUjn6cE4r0vfWdlyqevZk0V2/3LVKOTFRicrVB1P6886LMc0zoCd9G0wN3jIyhVlJG3NfOCjKbp/Q47L3jXOL1YRwoplPYbF9DD7O3hp5lajd/VW9daArava4Bvcat2QmDJXjxp4aEnFjnmVU33LE8sYkEr/9xQGKBUcaifk2Wj8zpvTFYH+AOQdUiVQxxWvfWnIsXRlfT6a/VjNi70sfjPGq7senqgoMSGM/wJ7MWcjKZaKU3hh80uyLVPMCExb5HpCa1rXE7UVeyZow5a1LgGrkMcfTOWvt/cP0nMwXvsnYxSLNrV1GOysvdKhnhAtqIcA9Zci8ddV5H3oR1RY/roQwWac5PrD/z5q5HchXhebkqdjDWXS/VrXnRi74qFCRmOpC83e7E8hD+0DPXdfrLzRoY9Pvpvvsgpc4k2YBTVVhLfKwqAsTAkIrI/Ip3u68bJxRypWD05aUPZ7Gfy9jeQQLDIdMRUiogicc07R3Nz0SW/kYlkqVGb93IfWAtUWNNHnVglNEL0oP24tieKVsqcOSO04YRshXvBrF70o8RztN+w7RzuUj7oc39E1zbxIxzOEdJV8/l9gNFOK21lnFLRMgisTQPr1IlgHTZy3ZQCBLxwvnziNilt3ZSAsD6Bz2+2ZRE+PoP0fOx/qeu+nmY/gLF5Asrp09A== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(346002)(136003)(376002)(39860400002)(396003)(451199018)(46966006)(36840700001)(40470700004)(110136005)(2616005)(36860700001)(47076005)(336012)(426003)(36756003)(7636003)(55016003)(6666004)(107886003)(16526019)(186003)(6286002)(40480700001)(26005)(478600001)(356005)(7696005)(1076003)(82740400003)(40460700003)(8676002)(70586007)(41300700001)(2906002)(70206006)(4326008)(86362001)(316002)(82310400005)(83380400001)(5660300002)(8936002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2023 12:57:47.0291 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f815fefa-c3b9-4f52-8982-08db0e8b123d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT069.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7968 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add HWS modify IPv6 protocol implementation. Signed-off-by: Rongwei Liu Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_prm.h | 1 + drivers/net/mlx5/mlx5_flow_dv.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index d93b0bfbae..c05bce714a 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -760,6 +760,7 @@ enum mlx5_modification_field { MLX5_MODI_TUNNEL_HDR_DW_1 = 0x75, MLX5_MODI_GTPU_FIRST_EXT_DW_0 = 0x76, MLX5_MODI_HASH_RESULT = 0x81, + MLX5_MODI_OUT_IPV6_NEXT_HDR = 0x4A, }; /* Total number of metadata reg_c's. */ diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 9e5db6b945..f93dd4073c 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -1357,6 +1357,7 @@ mlx5_flow_item_field_width(struct rte_eth_dev *dev, case RTE_FLOW_FIELD_IPV6_DSCP: return 6; case RTE_FLOW_FIELD_IPV6_HOPLIMIT: + case RTE_FLOW_FIELD_IPV6_PROTO: return 8; case RTE_FLOW_FIELD_IPV6_SRC: case RTE_FLOW_FIELD_IPV6_DST: @@ -1883,6 +1884,15 @@ mlx5_flow_field_id_to_modify_info info[idx].offset = data->offset; } break; + case RTE_FLOW_FIELD_IPV6_PROTO: + MLX5_ASSERT(data->offset + width <= 8); + off_be = 8 - (data->offset + width); + info[idx] = (struct field_modify_info){1, 0, MLX5_MODI_OUT_IPV6_NEXT_HDR}; + if (mask) + mask[idx] = flow_modify_info_mask_8(width, off_be); + else + info[idx].offset = off_be; + break; case RTE_FLOW_FIELD_POINTER: case RTE_FLOW_FIELD_VALUE: default: From patchwork Tue Feb 14 12:57:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: rongwei liu X-Patchwork-Id: 123892 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8322A41C49; Tue, 14 Feb 2023 13:58:11 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5D01842D8E; Tue, 14 Feb 2023 13:57:59 +0100 (CET) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2088.outbound.protection.outlook.com [40.107.94.88]) by mails.dpdk.org (Postfix) with ESMTP id 31D5542DAF for ; Tue, 14 Feb 2023 13:57:58 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=G+RcxdF0PCAyyuBN/pKknNc9m8mxy59GdtHr1rXW1YR/3fYybEjm9bapnyuoL7v42Xn4FylxzE5LloIrB1Mk4F7ZM4WQjd1FVQ88D7brwFJFwBQK5mfL1Eo2wQMjQSILH+WTq7W0ZDw6masfVfgdLT736M7e8/zqL0ZVI5SRRoZ6SMyfUWa+nBBoVZw9tgYgRYFQdhD4RORldEFlU+vbWUdoRqtr+jKb6KYAedIBkFa1QXbKQrkssITpEW+Ia1yi02u0Qob4jDiaDcmnwqU/shhHnjkhZNeLBNmfCxFdvl3TiGPtsyED/hlResF2js2iSmMqsX0reLArdIGYppz7hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ZeJHXr07Q20u+RWvYD30G2wuDAUN6GNFTnUBfxJJTAE=; b=IvTtnzzD7UuHCuuWkr1yYf3mwfan4+3feBmSI4R/3wW8jQrxCiCO49WK2Al9+gqYnoU+rgg9Fn1EfDZuzmvrvS/1h7QuWLtlbVbSH2dro9Zfts6emJUk5BZeZjnA00UaWC3Gzd0tGRPRCPFi9Y6EulFQfaIO3n+M5iJdkMmjUPhRFUh2m6BFV8Tq8r0h6R8sic13dOH7XFJqBaXQGTOQHH+Vkv9p3KPsAjaFbj2JHu6hwa+3DUys4Tq2nU523OTXc9wKyb5n0ibf25LcYv1o1swgRbGDIqmFlfMX42ypZ7KaMZA49C4MrH8lBRV6afTJSOzk9Pg9tpYZvHYymgyaCQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZeJHXr07Q20u+RWvYD30G2wuDAUN6GNFTnUBfxJJTAE=; b=nk2QkzBqWj1v0eT7u8tgVMzF8p9+AKegxVwyAQC+v/DmvfRZCMf6FoFb7w60/SOb9IbDK5LUaBB9/kgSZO3mxnP6OK+hB54fLo60sKkfWDfm4DUFDaabQzwQQAbhzi2SJdvGa+dIxEGOcNBbk3mdjk35mJbWorxhQ9st9MYLWbGz9gJh3O2y3edeeFvDZ3o7ijs1OW9Ty+CF0Q6/xDMJECeg+WJZ2q7EWov5GBWeo0t4k5W0CtpyUFdt7h7srYu4VkUb2qISmlQ5ecA2JVpjfHER33Zu4Jgdwi+pPYZqMxffcV72L0wYic6Cc7m/79TQ8vF1I1y1Ssr+6al9hNiGZA== Received: from DM6PR13CA0046.namprd13.prod.outlook.com (2603:10b6:5:134::23) by DS0PR12MB8415.namprd12.prod.outlook.com (2603:10b6:8:fc::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.22; Tue, 14 Feb 2023 12:57:55 +0000 Received: from DM6NAM11FT108.eop-nam11.prod.protection.outlook.com (2603:10b6:5:134:cafe::c9) by DM6PR13CA0046.outlook.office365.com (2603:10b6:5:134::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6111.10 via Frontend Transport; Tue, 14 Feb 2023 12:57:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT108.mail.protection.outlook.com (10.13.172.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6086.24 via Frontend Transport; Tue, 14 Feb 2023 12:57:55 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 14 Feb 2023 04:57:40 -0800 Received: from nvidia.com (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Tue, 14 Feb 2023 04:57:37 -0800 From: Rongwei Liu To: , , , , CC: , Ferruh Yigit Subject: [PATCH v3 5/5] doc/mlx5: add IPv6 routing extension matching docs Date: Tue, 14 Feb 2023 14:57:11 +0200 Message-ID: <20230214125711.3791966-6-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230214125711.3791966-1-rongweil@nvidia.com> References: <20230213113747.3677487-2-rongweil@nvidia.com> <20230214125711.3791966-1-rongweil@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT108:EE_|DS0PR12MB8415:EE_ X-MS-Office365-Filtering-Correlation-Id: 1927f384-3c46-40fb-32dd-08db0e8b1729 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZpCNeFlDf1bilX3bU3/xOpcQNrZfzq03MfFaJ+ecKV8apdiEuvj5Clrf1xP3iFl2lqG61AlrBzGpFm0hz5oSPXNnY2NgoFOVH4QViQ4QneOBElGzxItWsQAN4tHjL+3zeBUJRWuU02yhXVLVoqhR3VbsBGbRuNoDppVmwkSW7bSzVcg3reOl4VR2wjJdaMS8oG7mlxAK+Kh2WC/i5SrEEsMAd7p7au2hU2S5J/AWFdJK+cSJX2f6l8L98cXTmE4b9d4Bn1TTmgS6/zp9gn1XVBLzAeIG/SxybIz7uibb+6amIugeqjZLxZHNiTdfaKpuvVKSE/Iya1aQoI+NF8uJKjSWwxE3OKfPGBkPayZH6qB2yH/okxOcDNac/XV+rU9hFFeJR1mbASOZH1pdx50Y/ibCXcCOMZodSi9+psoJnSuxP9BZuFyF8T7uACCRV4pf1u9rWnvUuw6UPYueZ9MWC+IuXhgHp6g+So0t8JZpvwXfLtvDTPUFN4f+fUybmGrWYPHM25LjasZHREHj1jZwTHdhRvLviwNXXlY+OaFkWPMhSLpdYumxeI+Kqafwrj3pRvjY82nNc/CjsEdNyOCjl2df9TUvTgc1zBArh+KGmlNR1EOVWxdBXzqH5r3nyNZ068rqMnoBsUYl2H4Dnyb52xJquMsy5ZGrlpFzrnRyaoyUQ3+au7QMtT+fdtGnpmWGwhNru8gDXW6CIrNXcbsJmw== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(136003)(376002)(39860400002)(346002)(396003)(451199018)(46966006)(40470700004)(36840700001)(5660300002)(70586007)(86362001)(8936002)(41300700001)(70206006)(110136005)(54906003)(4326008)(8676002)(2906002)(316002)(356005)(40480700001)(82740400003)(7636003)(82310400005)(55016003)(7696005)(6666004)(186003)(36860700001)(47076005)(478600001)(83380400001)(1076003)(2616005)(6286002)(16526019)(26005)(426003)(36756003)(40460700003)(336012); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2023 12:57:55.3469 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1927f384-3c46-40fb-32dd-08db0e8b1729 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT108.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8415 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Update mlx5 related document on IPv6 routing extension header matching. Signed-off-by: Rongwei Liu Acked-by: Viacheslav Ovsiienko --- doc/guides/nics/features/default.ini | 1 + doc/guides/nics/features/mlx5.ini | 1 + doc/guides/nics/mlx5.rst | 10 ++++++++++ 3 files changed, 12 insertions(+) diff --git a/doc/guides/nics/features/default.ini b/doc/guides/nics/features/default.ini index 976a020985..b1ad3bdca0 100644 --- a/doc/guides/nics/features/default.ini +++ b/doc/guides/nics/features/default.ini @@ -143,6 +143,7 @@ udp = vlan = vxlan = vxlan_gpe = +ipv6_routing_ext = [rte_flow actions] age = diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini index eb016f34da..dac5ee5579 100644 --- a/doc/guides/nics/features/mlx5.ini +++ b/doc/guides/nics/features/mlx5.ini @@ -89,6 +89,7 @@ vlan = Y vxlan = Y vxlan_gpe = Y represented_port = Y +ipv6_routing_ext = Y [rte_flow actions] age = I diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 9c6f1cca19..ee2df66e77 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -106,6 +106,7 @@ Features - Sub-Function representors. - Sub-Function. - Matching on represented port. +- Matching on IPv6 routing extension header. Limitations @@ -174,6 +175,7 @@ Limitations - ``-EAGAIN`` for ``rte_eth_dev_start()``. - ``-EBUSY`` for ``rte_eth_dev_stop()``. + - Matching on ICMP6 following IPv6 routing extension header, should match ipv6_routing_ext_next_hdr instead of ICMP6. - When using Verbs flow engine (``dv_flow_en`` = 0), flow pattern without any specific VLAN will match for VLAN packets as well: @@ -274,6 +276,14 @@ Limitations extension header type = 0x85). - Match on GTP extension header is not supported in group 0. +- Match on IPv6 routing extension header supports the following fields only: + + - type + - next_hdr + - segments_left + + Only supports HW steering. (``dv_flow_en=2``) + - Flex item: - Hardware support: BlueField-2.