From patchwork Wed Feb 22 21:23:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 124405 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 40A6D41D43; Wed, 22 Feb 2023 22:23:29 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EC99C430CA; Wed, 22 Feb 2023 22:23:28 +0100 (CET) Received: from NAM02-DM3-obe.outbound.protection.outlook.com (mail-dm3nam02on2064.outbound.protection.outlook.com [40.107.95.64]) by mails.dpdk.org (Postfix) with ESMTP id C67204021F for ; Wed, 22 Feb 2023 22:23:27 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=VUbzUnBGtdn5ewHjLNADiret14ay9L7mlQzxTcYnnwm9N/dCTZAAF9Vb4qrU+UdVF8P67TW+QDBWxLMHogYmSbhup+FIH+bVwDqvZNiCZi8ADhmS2/96NLRHG+Grfe3v8p6VOqoySadqYVWQvZ9+HshBA53Pk8lS+hWwsjkgS0IzughRo8WGkLY37x30Ki548Qn93NUDD7OdUtgezcnREJuYSgFyjWR6hPW9vIy5paqG1CcP1XHeD40/yGMJRvygV6NosGv1JOu4xn7bgGZiKP+9UUq+Qz97cDw8qfz6J9UzL1LuRMr190aWknCOCtx3OKCJc1msPNGpc1S1F9aljw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QoEm9Mk08gstLiUyS9kOohc0JHDqGE5B3zJJQUcf4TY=; b=OdJR1mCzDdgFmzoOexu8xY6GZoeuIF7zF9LKCKtmMyoBcA/qY619DraO5JROoRQ92hQHe97nKeY3d0zWh5LRllVjOUVo6zQK6GVt/JV168L1Geum+MMdyHwWBKC/JQee0TbN29P+FBNU6ymJGAsaV9IIXx7arVs89vAKmFinwSbad9TvIupIkB/ZX/lQvOvcJbLwRd9YkiRlNX90tyfFh1+sBIB64U4NksYP184y1VOeGARzWXzt0SQ25nQSCyWfPtb/vf3jGwfAieCy+Q7TMROCpmdtIC/2QuHys5TSFLS3GvL7h6HUbp9Xgx3ZVYQLdOFykHXXNg41Di0iRdtvKQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.232) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QoEm9Mk08gstLiUyS9kOohc0JHDqGE5B3zJJQUcf4TY=; b=bBnxwnNKzdPVLMeeISVLMuhcHUN9lyWIk5mEcvGcqzbZ5h2e6MdvEaJNMAir3ilIbJSfdptGqSsqR8KKwK8wyRDFyyIRu4tXTJLqJaBQNS0CEVMNCRXK7h07k4CPrk3LMYN3HR01Win092d2WtIuIsNasr4QOKRCppL+5LyrB5fggMLBLA3Ffab4hdKjNJDPWWCNV7g2OYjPFWf0Kn9bFlXUIE0hdJKHNu4aCvOAEduUIaOx47XiNMZAY4wxCI7MOSLhiNjYwgm90+lpgupsRWIIUZazlaP3r8Nc2wAIqDwxI97VXcnsxW2mfzc+HlUALINNAqAvfgAZjT1pvkBEgQ== Received: from BN6PR17CA0026.namprd17.prod.outlook.com (2603:10b6:405:75::15) by MN2PR12MB4287.namprd12.prod.outlook.com (2603:10b6:208:1dd::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6134.19; Wed, 22 Feb 2023 21:23:25 +0000 Received: from BN8NAM11FT030.eop-nam11.prod.protection.outlook.com (2603:10b6:405:75:cafe::22) by BN6PR17CA0026.outlook.office365.com (2603:10b6:405:75::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6134.19 via Frontend Transport; Wed, 22 Feb 2023 21:23:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.232) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.232 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.232) by BN8NAM11FT030.mail.protection.outlook.com (10.13.177.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6134.20 via Frontend Transport; Wed, 22 Feb 2023 21:23:25 +0000 Received: from drhqmail202.nvidia.com (10.126.190.181) by mail.nvidia.com (10.127.129.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 22 Feb 2023 13:23:18 -0800 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail202.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 22 Feb 2023 13:23:17 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36 via Frontend Transport; Wed, 22 Feb 2023 13:23:16 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Erez Shitrit Subject: [PATCH v2 1/2] net/mlx5/hws: support matching on MPLSoUDP Date: Wed, 22 Feb 2023 23:23:09 +0200 Message-ID: <20230222212310.3295762-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230222212310.3295762-1-michaelba@nvidia.com> References: <20230222212310.3295762-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT030:EE_|MN2PR12MB4287:EE_ X-MS-Office365-Filtering-Correlation-Id: a30db6a3-5ab5-4aec-6ce6-08db151b08b8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Z01kd1FtnPSNWbQSdKjS3hlxI5sB7h1e0I4ksoW3ff7Q4OwoPkI2UYfiI0AkadWkn7tUnblA2YcAYVatRvSrVAxujJosHd1oxMj3M0Ol8hVpxWfuwZ6mFgkU4UtJ9LYUsjSckX8PS1pTDVj+tKhDNnANeB7t0sAn6yKaiQvGjDmn9uTNsrs+FmGLZ5MZrHKfZTdn6iAzuxz+hU3F2HuAHAD3WbNWwKrnc0o81aul1AGJ5+e58BfAHOqg8OGsw6tXH6iZl0VjtrLAoKv3gqGVRF/WZ0G4SN0iojwIpS1o+rz1jLUa9vrUmL2LxyQMmoGrgNSLGJ0cfRh66UoHV/U5Up1o5nLG6ekYcA03J+ZhzKJICCsBZhKyROLeQC2RJWAJeVDcflH6xD4C2xrDvlz1MyNAKAO315myqmiT6umnXFxDwCL0HUbNMKW0HiywL6CFZv74gdLlRii4Nss3OvjS+5Kc5LpHAIg+0mdW9HCzsfYcoenyhTwNTw5FYgSv/VsXgu944ITW6GG0o4mUK7zW9EYzVjFfw+hwOcK5m/d171R+S9Q4PDuQg80QHkW29Gfmg8uK4eNPmvVejOTLfbZqaihM7MKuJCR+BZEimYebEEOmnWdkTDaTqUxcuYi8x9bJ9oJ+X5FBOmMrmW7GbDsF2/eG7F0GS6LUh7jUmL5zml8PwoHrfg/cZKYvCBzFJU6HZ/iN2HtgH+0Bdw3Rp6NhLKPCSrHVOgUAEIN75I4y2ZM= X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(136003)(396003)(39860400002)(376002)(346002)(451199018)(40470700004)(46966006)(36840700001)(86362001)(82310400005)(316002)(2616005)(54906003)(40460700003)(6286002)(70206006)(36860700001)(70586007)(1076003)(5660300002)(2906002)(4326008)(6916009)(8676002)(34020700004)(41300700001)(47076005)(6666004)(26005)(186003)(107886003)(426003)(478600001)(7696005)(55016003)(40480700001)(36756003)(336012)(82740400003)(7636003)(356005)(8936002)(83380400001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Feb 2023 21:23:25.5630 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a30db6a3-5ab5-4aec-6ce6-08db151b08b8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4287 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Erez Shitrit Add support for matching MPLS labels while it is under UDP protocol. Matching up to 5 MPLS labels with or without the MPLS value. Signed-off-by: Erez Shitrit --- drivers/net/mlx5/hws/mlx5dr_definer.c | 183 +++++++++++++++++++++++++- drivers/net/mlx5/hws/mlx5dr_definer.h | 32 ++++- 2 files changed, 212 insertions(+), 3 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 6374f9df33..4bfc2caed0 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -9,6 +9,8 @@ #define ETH_TYPE_IPV4_VXLAN 0x0800 #define ETH_TYPE_IPV6_VXLAN 0x86DD #define ETH_VXLAN_DEFAULT_PORT 4789 +#define IP_UDP_PORT_MPLS 6635 +#define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS) #define STE_NO_VLAN 0x0 #define STE_SVLAN 0x1 @@ -104,6 +106,8 @@ struct mlx5dr_definer_conv_data { struct mlx5dr_definer_fc *fc; uint8_t relaxed; uint8_t tunnel; + uint8_t mpls_idx; + enum rte_flow_item_type last_item; }; /* Xmacro used to create generic item setter from items */ @@ -154,6 +158,7 @@ struct mlx5dr_definer_conv_data { X(SET, gtp_ext_hdr_qfi, v->hdr.qfi, rte_flow_item_gtp_psc) \ X(SET, vxlan_flags, v->flags, rte_flow_item_vxlan) \ X(SET, vxlan_udp_port, ETH_VXLAN_DEFAULT_PORT, rte_flow_item_vxlan) \ + X(SET, mpls_udp_port, IP_UDP_PORT_MPLS, rte_flow_item_mpls) \ X(SET, source_qp, v->queue, mlx5_rte_flow_item_sq) \ X(SET, tag, v->data, rte_flow_item_tag) \ X(SET, metadata, v->data, rte_flow_item_meta) \ @@ -457,6 +462,89 @@ mlx5dr_definer_vport_set(struct mlx5dr_definer_fc *fc, DR_SET(tag, regc_value, fc->byte_off, fc->bit_off, fc->bit_mask); } +static struct mlx5dr_definer_fc * +mlx5dr_definer_get_mpls_fc(struct mlx5dr_definer_conv_data *cd, bool inner) +{ + uint8_t mpls_idx = cd->mpls_idx; + struct mlx5dr_definer_fc *fc; + + switch (mpls_idx) { + case 0: + fc = &cd->fc[DR_CALC_FNAME(MPLS0, inner)]; + DR_CALC_SET_HDR(fc, mpls_inner, mpls0_label); + break; + case 1: + fc = &cd->fc[DR_CALC_FNAME(MPLS1, inner)]; + DR_CALC_SET_HDR(fc, mpls_inner, mpls1_label); + break; + case 2: + fc = &cd->fc[DR_CALC_FNAME(MPLS2, inner)]; + DR_CALC_SET_HDR(fc, mpls_inner, mpls2_label); + break; + case 3: + fc = &cd->fc[DR_CALC_FNAME(MPLS3, inner)]; + DR_CALC_SET_HDR(fc, mpls_inner, mpls3_label); + break; + case 4: + fc = &cd->fc[DR_CALC_FNAME(MPLS4, inner)]; + DR_CALC_SET_HDR(fc, mpls_inner, mpls4_label); + break; + default: + rte_errno = ENOTSUP; + DR_LOG(ERR, "MPLS index %d is not supported\n", mpls_idx); + return NULL; + } + + return fc; +} + +static struct mlx5dr_definer_fc * +mlx5dr_definer_get_mpls_oks_fc(struct mlx5dr_definer_conv_data *cd, bool inner) +{ + uint8_t mpls_idx = cd->mpls_idx; + struct mlx5dr_definer_fc *fc; + + switch (mpls_idx) { + case 0: + fc = &cd->fc[DR_CALC_FNAME(OKS2_MPLS0, inner)]; + DR_CALC_SET_HDR(fc, oks2, second_mpls0_qualifier); + break; + case 1: + fc = &cd->fc[DR_CALC_FNAME(OKS2_MPLS1, inner)]; + DR_CALC_SET_HDR(fc, oks2, second_mpls1_qualifier); + break; + case 2: + fc = &cd->fc[DR_CALC_FNAME(OKS2_MPLS2, inner)]; + DR_CALC_SET_HDR(fc, oks2, second_mpls2_qualifier); + break; + case 3: + fc = &cd->fc[DR_CALC_FNAME(OKS2_MPLS3, inner)]; + DR_CALC_SET_HDR(fc, oks2, second_mpls3_qualifier); + break; + case 4: + fc = &cd->fc[DR_CALC_FNAME(OKS2_MPLS4, inner)]; + DR_CALC_SET_HDR(fc, oks2, second_mpls4_qualifier); + break; + default: + rte_errno = ENOTSUP; + DR_LOG(ERR, "MPLS index %d is not supported\n", mpls_idx); + return NULL; + } + + return fc; +} + +static void +mlx5dr_definer_mpls_label_set(struct mlx5dr_definer_fc *fc, + const void *item_spec, + uint8_t *tag) +{ + const struct rte_flow_item_mpls *v = item_spec; + + memcpy(tag + fc->byte_off, v->label_tc_s, sizeof(v->label_tc_s)); + memcpy(tag + fc->byte_off + sizeof(v->label_tc_s), &v->ttl, sizeof(v->ttl)); +} + static int mlx5dr_definer_conv_item_eth(struct mlx5dr_definer_conv_data *cd, struct rte_flow_item *item, @@ -1157,6 +1245,74 @@ mlx5dr_definer_conv_item_vxlan(struct mlx5dr_definer_conv_data *cd, return 0; } +static int +mlx5dr_definer_conv_item_mpls(struct mlx5dr_definer_conv_data *cd, + struct rte_flow_item *item, + int item_idx) +{ + const struct rte_flow_item_mpls *m = item->mask; + struct mlx5dr_definer_fc *fc; + bool inner = cd->tunnel; + + if (inner) { + DR_LOG(ERR, "Inner MPLS item not supported"); + rte_errno = ENOTSUP; + return rte_errno; + } + + if (cd->relaxed) { + DR_LOG(ERR, "Relaxed mode is not supported"); + rte_errno = ENOTSUP; + return rte_errno; + } + + /* Currently support only MPLSoUDP */ + if (cd->last_item != RTE_FLOW_ITEM_TYPE_UDP && + cd->last_item != RTE_FLOW_ITEM_TYPE_MPLS) { + DR_LOG(ERR, "MPLS supported only after UDP"); + rte_errno = ENOTSUP; + return rte_errno; + } + + /* In order to match on MPLS we must match on ip_protocol and l4_dport. */ + fc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, false)]; + if (!fc->tag_set) { + fc->item_idx = item_idx; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->tag_set = &mlx5dr_definer_udp_protocol_set; + DR_CALC_SET(fc, eth_l2, l4_type_bwc, false); + } + + fc = &cd->fc[DR_CALC_FNAME(L4_DPORT, false)]; + if (!fc->tag_set) { + fc->item_idx = item_idx; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->tag_set = &mlx5dr_definer_mpls_udp_port_set; + DR_CALC_SET(fc, eth_l4, destination_port, false); + } + + if (m && (!is_mem_zero(m->label_tc_s, 3) || m->ttl)) { + /* According to HW MPLSoUDP is handled as inner */ + fc = mlx5dr_definer_get_mpls_fc(cd, true); + if (!fc) + return rte_errno; + + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_mpls_label_set; + } else { /* Mask relevant oks2 bit, indicates MPLS label exists. + * According to HW MPLSoUDP is handled as inner + */ + fc = mlx5dr_definer_get_mpls_oks_fc(cd, true); + if (!fc) + return rte_errno; + + fc->item_idx = item_idx; + fc->tag_set = mlx5dr_definer_ones_set; + } + + return 0; +} + static struct mlx5dr_definer_fc * mlx5dr_definer_get_register_fc(struct mlx5dr_definer_conv_data *cd, int reg) { @@ -1782,6 +1938,24 @@ mlx5dr_definer_conv_item_esp(struct mlx5dr_definer_conv_data *cd, return 0; } +static void mlx5dr_definer_set_conv_tunnel(enum rte_flow_item_type cur_type, + uint64_t item_flags, + struct mlx5dr_definer_conv_data *cd) +{ + /* already tunnel nothing to change */ + if (cd->tunnel) + return; + + /* we can have more than one MPLS label at each level (inner/outer), so + * consider tunnel only when it is already under tunnel or if we moved to the + * second MPLS level. + */ + if (cur_type != RTE_FLOW_ITEM_TYPE_MPLS) + cd->tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); + else + cd->tunnel = !!(item_flags & DR_FLOW_LAYER_TUNNEL_NO_MPLS); +} + static int mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, struct mlx5dr_match_template *mt, @@ -1799,7 +1973,7 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, /* Collect all RTE fields to the field array and set header layout */ for (i = 0; items->type != RTE_FLOW_ITEM_TYPE_END; i++, items++) { - cd.tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); + mlx5dr_definer_set_conv_tunnel(items->type, item_flags, &cd); ret = mlx5dr_definer_check_item_range_supp(items); if (ret) @@ -1913,12 +2087,19 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, ret = mlx5dr_definer_conv_item_esp(&cd, items, i); item_flags |= MLX5_FLOW_ITEM_ESP; break; + case RTE_FLOW_ITEM_TYPE_MPLS: + ret = mlx5dr_definer_conv_item_mpls(&cd, items, i); + item_flags |= MLX5_FLOW_LAYER_MPLS; + cd.mpls_idx++; + break; default: DR_LOG(ERR, "Unsupported item type %d", items->type); rte_errno = ENOTSUP; return rte_errno; } + cd.last_item = items->type; + if (ret) { DR_LOG(ERR, "Failed processing item type: %d", items->type); return ret; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index 4bf7bd8df3..0cd83db756 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -114,6 +114,26 @@ enum mlx5dr_definer_fname { MLX5DR_DEFINER_FNAME_ICMP_DW2, MLX5DR_DEFINER_FNAME_ESP_SPI, MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER, + MLX5DR_DEFINER_FNAME_MPLS0_O, + MLX5DR_DEFINER_FNAME_MPLS1_O, + MLX5DR_DEFINER_FNAME_MPLS2_O, + MLX5DR_DEFINER_FNAME_MPLS3_O, + MLX5DR_DEFINER_FNAME_MPLS4_O, + MLX5DR_DEFINER_FNAME_MPLS0_I, + MLX5DR_DEFINER_FNAME_MPLS1_I, + MLX5DR_DEFINER_FNAME_MPLS2_I, + MLX5DR_DEFINER_FNAME_MPLS3_I, + MLX5DR_DEFINER_FNAME_MPLS4_I, + MLX5DR_DEFINER_FNAME_OKS2_MPLS0_O, + MLX5DR_DEFINER_FNAME_OKS2_MPLS1_O, + MLX5DR_DEFINER_FNAME_OKS2_MPLS2_O, + MLX5DR_DEFINER_FNAME_OKS2_MPLS3_O, + MLX5DR_DEFINER_FNAME_OKS2_MPLS4_O, + MLX5DR_DEFINER_FNAME_OKS2_MPLS0_I, + MLX5DR_DEFINER_FNAME_OKS2_MPLS1_I, + MLX5DR_DEFINER_FNAME_OKS2_MPLS2_I, + MLX5DR_DEFINER_FNAME_OKS2_MPLS3_I, + MLX5DR_DEFINER_FNAME_OKS2_MPLS4_I, MLX5DR_DEFINER_FNAME_MAX, }; @@ -434,6 +454,14 @@ struct mlx5_ifc_definer_hl_registers_bits { u8 register_c_1[0x20]; }; +struct mlx5_ifc_definer_hl_mpls_bits { + u8 mpls0_label[0x20]; + u8 mpls1_label[0x20]; + u8 mpls2_label[0x20]; + u8 mpls3_label[0x20]; + u8 mpls4_label[0x20]; +}; + struct mlx5_ifc_definer_hl_bits { struct mlx5_ifc_definer_hl_eth_l2_bits eth_l2_outer; struct mlx5_ifc_definer_hl_eth_l2_bits eth_l2_inner; @@ -462,8 +490,8 @@ struct mlx5_ifc_definer_hl_bits { u8 unsupported_udp_misc_inner[0x20]; struct mlx5_ifc_definer_tcp_icmp_header_bits tcp_icmp; struct mlx5_ifc_definer_hl_tunnel_header_bits tunnel_header; - u8 unsupported_mpls_outer[0xa0]; - u8 unsupported_mpls_inner[0xa0]; + struct mlx5_ifc_definer_hl_mpls_bits mpls_outer; + struct mlx5_ifc_definer_hl_mpls_bits mpls_inner; u8 unsupported_config_headers_outer[0x80]; u8 unsupported_config_headers_inner[0x80]; u8 unsupported_random_number[0x20]; From patchwork Wed Feb 22 21:23:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 124407 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A98B041D43; Wed, 22 Feb 2023 22:23:47 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9C3214315B; Wed, 22 Feb 2023 22:23:47 +0100 (CET) Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2044.outbound.protection.outlook.com [40.107.93.44]) by mails.dpdk.org (Postfix) with ESMTP id A97C343135 for ; Wed, 22 Feb 2023 22:23:46 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JOWPagl8NB+JmLHBoREXipjTsn9dyWaqS5uliR7uZ3XkJD7MhIsmMc564UgRhLO7dCCleyU5yzE+YiZ6+HJl0XHBBheEuKWM4zmlYGy3EdNaCSP3oOfJ9b89wHnyO+KYV2YI4TPof7YHW2bvgwG5vmK/Fq5d6AZqx/4htfl7ESh0N/z5GVpBHsbmw0yCGN1Sa6l6DtOc+sZ0O6myd/nl27NPbo1S0Ij6JEXJwelLIM8lQSOPLhb/z9lBl/FaYwDPgSiJ4qs3eJCGsn8Uvi1MppC6Fhhk+1XHOZq1P4pZl+o7xZcnw/iMlnhNdjw8KzTM6Wnpi/nLc3PrQ4bI/Yhl+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=omB+2giC3e7IITgOdRmD7cGjck4u9zuo3gExbEMrNLc=; b=RLX/1SjbsVkr2rqcmf7nYP2+FBt5SmPgJo/zA32akEQUWvlsB7qXu34YGqyx28AdTJ8BdVVxslzEITwILhJPfoMCRHQLiykXStlcWbRY95+NrTilpzmTYwC9IXxfNfM/aLNdxcRpbZDd1EZoF5rAcksCCsLlRYT+y9o8+tvtzAVndjnVpswhVGX9jSDCEFcMvfmnH5XRcWOgwIUSJ7DUkaEQ24+/2Y15+ijjqTWNJSgyygZdLGldY/xXGjMPSnAfzL96GvewajIhFZvlYOhb1q7zGiDeNFp5zbCHv6apYCL02W89h1Zdjk+HW/HtPCMs6hUyWwMMQTP7Rck9V5+lEg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=omB+2giC3e7IITgOdRmD7cGjck4u9zuo3gExbEMrNLc=; b=JlSIVrtmMIvZYxHY7oOo4pABIgFjQLyDSkhPi6c+8gWD1Kg23aYGQLVbaOUEwAD8p9p+Gv0HYy1cihC3aFd8A1YivTLV43y6XA4mgxTJaLKAC6YwIxQt7jbUsqzdnt7rZvNrTZSFTqsLrSg7dL2Yq1wLTKP7uipvc2pvrJoRaDr5sV4OKjWQtmBP2VWC6KMwOkntJqRi0kvvaoeMfFhpv3X1Qi0vF33G9PP/AJWGIr+/jI+2Zo1DJu3h6MOeuNcGQlffERirPnioZH9hPknvdAwgfIagS6m96/7puX2NEt8wmwkoV5F9H+eg5UajthDRZEalyb9l3aRE21vRFaxbTA== Received: from BN0PR02CA0059.namprd02.prod.outlook.com (2603:10b6:408:e5::34) by PH7PR12MB7211.namprd12.prod.outlook.com (2603:10b6:510:206::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6111.21; Wed, 22 Feb 2023 21:23:45 +0000 Received: from BN8NAM11FT102.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e5:cafe::42) by BN0PR02CA0059.outlook.office365.com (2603:10b6:408:e5::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6111.21 via Frontend Transport; Wed, 22 Feb 2023 21:23:44 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by BN8NAM11FT102.mail.protection.outlook.com (10.13.177.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6134.21 via Frontend Transport; Wed, 22 Feb 2023 21:23:44 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 22 Feb 2023 13:23:20 -0800 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Wed, 22 Feb 2023 13:23:20 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36 via Frontend Transport; Wed, 22 Feb 2023 13:23:18 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam Subject: [PATCH v2 2/2] net/mlx5: add MPLS tunnel support for HWS Date: Wed, 22 Feb 2023 23:23:10 +0200 Message-ID: <20230222212310.3295762-3-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230222212310.3295762-1-michaelba@nvidia.com> References: <20230222212310.3295762-1-michaelba@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT102:EE_|PH7PR12MB7211:EE_ X-MS-Office365-Filtering-Correlation-Id: 9e6545d5-7ae9-476c-10fb-08db151b13ed X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /XJbgSi1iTYDya49EFa6Ycmucp7E9m9sOhmUHKc/O+7JNDeaM/urB0gZpQ9IaAM5EWBz/DtYoItFCPZxmnRFcUWamOzQ76s2LYpeglSzR4smqFcDPxC/j77xlrHWuf1n9X3ynTo+W1HB6Ee4moeiXSOefEr7lbVFkxoQI5bxYF4KKOhB0z9pBHUIHMQVMB+dt2lGPHvpmf3lwGq2CfJVaOc+NXAm2d/ihAOidulAGq1ny2tIvYK5kJYu5K5atDQaGyVzV16HAUKewwYN0QDktYzcWq8xnqxZsL6MX2J5/EHK5TLPpSflEMz16Vy63gTW17ouZt7UobM0y177yj7ehgKc0XfYCsDLAi44mPWPfWGZsNbRhtJgm19dHEPY/wmyZYWXwNGgu64thiWIwcuCw7/z+4j/QzwrsQ9xQf2SETLeDlFKlMqhbxBIs00qKB6X1mRipaY/r4s93C49w5Auaqgl9Lxip28tJuO3ljU4x2jyyKSIjiVXDHZ4whjgv0pwPAmOtLODcwQrwd7wC0koBJDDXu6cnHvk0Jq67TugIpuH0lMAdvbO0qIRZDiPrD8VAFb6ypxVOWGQiWO2UM4Vg+m/YxVivQJ9osxgEESlYtdfvFDdWXkToSsOJFq3+yijZ048gIwaIiBuBQhbru9ncGhcBNHEjiXo76inNHzsBrwiu9GT/o7BcQL11xqiJLby0L9tkBVWsxBkaHl+8B2KUekozWqGnDIraVT6GeZKPsA= X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230025)(4636009)(376002)(39860400002)(346002)(396003)(136003)(451199018)(36840700001)(46966006)(40470700004)(2906002)(6286002)(186003)(7636003)(82740400003)(26005)(1076003)(8936002)(356005)(6666004)(107886003)(40460700003)(478600001)(36860700001)(70586007)(70206006)(47076005)(2616005)(34020700004)(5660300002)(426003)(41300700001)(86362001)(40480700001)(336012)(36756003)(316002)(7696005)(83380400001)(4326008)(6916009)(8676002)(55016003)(82310400005)(54906003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Feb 2023 21:23:44.3629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e6545d5-7ae9-476c-10fb-08db151b13ed X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT102.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7211 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add support for MPLS tunnel item in HWS. Signed-off-by: Michael Baum Acked-by: Ori Kam --- doc/guides/nics/mlx5.rst | 4 ++++ doc/guides/rel_notes/release_23_03.rst | 1 + drivers/net/mlx5/mlx5_flow_hw.c | 1 + 3 files changed, 6 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index f9b3d43378..4142933b0d 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -245,6 +245,10 @@ Limitations - L3 VXLAN and VXLAN-GPE tunnels cannot be supported together with MPLSoGRE and MPLSoUDP. +- MPLSoGRE is not supported in HW steering (``dv_flow_en`` = 2). + +- MPLSoUDP with multiple MPLS headers is only supported in HW steering (``dv_flow_en`` = 2). + - Match on Geneve header supports the following fields only: - VNI diff --git a/doc/guides/rel_notes/release_23_03.rst b/doc/guides/rel_notes/release_23_03.rst index 2ca30b3b49..8a3988c033 100644 --- a/doc/guides/rel_notes/release_23_03.rst +++ b/doc/guides/rel_notes/release_23_03.rst @@ -114,6 +114,7 @@ New Features * **Updated NVIDIA mlx5 driver.** * Added support for matching on ICMPv6 ID and sequence fields. + * Added support for MPLSoUDP in hardware steering. * **Updated Wangxun ngbe driver.** diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index a9c7045a3e..80d4beeecd 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -4733,6 +4733,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, case RTE_FLOW_ITEM_TYPE_GTP: case RTE_FLOW_ITEM_TYPE_GTP_PSC: case RTE_FLOW_ITEM_TYPE_VXLAN: + case RTE_FLOW_ITEM_TYPE_MPLS: case MLX5_RTE_FLOW_ITEM_TYPE_SQ: case RTE_FLOW_ITEM_TYPE_GRE: case RTE_FLOW_ITEM_TYPE_GRE_KEY: