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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS1PEPF0000E643.mail.protection.outlook.com (10.167.17.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6156.12 via Frontend Transport; Sat, 25 Feb 2023 20:19:01 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sat, 25 Feb 2023 12:18:50 -0800 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sat, 25 Feb 2023 12:18:48 -0800 From: Dariusz Sosnowski To: Matan Azrad , Viacheslav Ovsiienko CC: , , Ori Kam Subject: [PATCH 1/2] net/mlx5: fix egress group translation in HWS Date: Sat, 25 Feb 2023 20:18:09 +0000 Message-ID: <20230225201810.10838-2-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230225201810.10838-1-dsosnowski@nvidia.com> References: <20230225201810.10838-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E643:EE_|CH0PR12MB5027:EE_ X-MS-Office365-Filtering-Correlation-Id: 840747f6-85cd-4d08-3331-08db176d8891 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Feb 2023 20:19:01.1586 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 840747f6-85cd-4d08-3331-08db176d8891 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E643.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5027 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org With HW Steering enabled creating egress template tables and egress flow rules on E-Switch setups is allowed. To enable it, PMD creates a set of default egress flow rules responsible for: - Storing representor ID (vport tag is used) in HW register. This is used for traffic source identification. - Copying software metadata to proper HW register to allow preserving metadata across domains. Structure of these flow rules and whether they are inserted depend on the device configuration. There are the following cases: 1. repr_matching=1 and dv_xmeta_en=4 - An egress flow rule in group 0 is created for each Tx queue; - Flow rule matching SQ number - fills unused REG_C_0 bits with vport tag, copies REG_A to REG_C_1 and jumps to group 1. 2. repr_matching=1 and dv_xmeta_en=0 - An egress flow rule in group 0 is created for each Tx queue; - Flow rule matching SQ number - fills unused REG_C_0 bits with vport tag and jumps to group 1. 3. repr_matching=0 and dv_xmeta_en=4 - A single egress flow rule in group 0 is created; - Flow rule matches all E-Switch manager TX traffic, copies REG_A to REG_C and jumps to group 1. 4. repr_matching=0 and dv_xmeta_en=0 - no default flow rules are added. When default egress flow rules are required, they are inserted in group 0 and this group is reserved for PMD purposes. User created template tables must be created in higher groups. As a result, on template table creation PMD is translating the provided group (incrementing it in that case). Before this patch, a condition used to check if translation of egress flow group is needed was incorrect. It did not allow translation if both representor matching AND extended metadata mode were enabled. This patch fixes this condition - translation is allowed if and only if representor matching OR extended metadata mode is enabled. Fixes: 483181f7b6dd ("net/mlx5: support device control of representor matching") Cc: stable@dpdk.org Signed-off-by: Dariusz Sosnowski Acked-by: Ori Kam Acked-by: Suanming Mou --- drivers/net/mlx5/mlx5_flow_hw.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index a9c7045a3e..d3d86fe24d 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -3260,14 +3260,18 @@ flow_hw_translate_group(struct rte_eth_dev *dev, "group index not supported"); *table_group = group + 1; } else if (config->dv_esw_en && - !(config->repr_matching && config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) && + (config->repr_matching || config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) && cfg->external && flow_attr->egress) { /* - * On E-Switch setups, egress group translation is not done if and only if - * representor matching is disabled and legacy metadata mode is selected. - * In all other cases, egree group 0 is reserved for representor tagging flows - * and metadata copy flows. + * On E-Switch setups, default egress flow rules are inserted to allow + * representor matching and/or preserving metadata across steering domains. + * These flow rules are inserted in group 0 and this group is reserved by PMD + * for these purposes. + * + * As a result, if representor matching or extended metadata mode is enabled, + * group provided by the user must be incremented to avoid inserting flow rules + * in group 0. */ if (group > MLX5_HW_MAX_EGRESS_GROUP) return rte_flow_error_set(error, EINVAL, From patchwork Sat Feb 25 20:18:10 2023 Content-Type: text/plain; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DS1PEPF0000E643.mail.protection.outlook.com (10.167.17.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6156.12 via Frontend Transport; Sat, 25 Feb 2023 20:19:02 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sat, 25 Feb 2023 12:18:54 -0800 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Sat, 25 Feb 2023 12:18:53 -0800 From: Dariusz Sosnowski To: Matan Azrad , Viacheslav Ovsiienko CC: , , Ori Kam Subject: [PATCH 2/2] net/mlx5: fix isolated mode when repr matching is disabled Date: Sat, 25 Feb 2023 20:18:10 +0000 Message-ID: <20230225201810.10838-3-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230225201810.10838-1-dsosnowski@nvidia.com> References: <20230225201810.10838-1-dsosnowski@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E643:EE_|CY5PR12MB6429:EE_ X-MS-Office365-Filtering-Correlation-Id: 1f3b39de-6213-443d-8bbf-08db176d896c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Feb 2023 20:19:02.6117 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f3b39de-6213-443d-8bbf-08db176d896c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E643.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6429 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org In HW steering mode, when running on an E-Switch setup, mlx5 PMD provides an ability to enable or disable representor matching (through `repr_matching_en` device argument). If representor matching is enabled, any ingress or egress flow rule, created on any port representor will match traffic related to that specific port. If it is disabled, flow rule created on one of the ports, will match traffic related to all ports. As a result, when representor matching is disabled, PMD cannot correctly create control flow rules for receiving default traffic according to port configuration. Since each port representor in the same switch domain, can have different port configuration and flow rules do not differentiate between ports, these flow rules cannot be correctly applied. In that case, each port works in de facto isolated mode. This patch makes sure that if representor matching is disabled, port is forced into isolated mode. Disabling flow isolated is forbidden. Fixes: 483181f7b6dd ("net/mlx5: support device control of representor matching") Cc: stable@dpdk.org Signed-off-by: Dariusz Sosnowski Acked-by: Ori Kam Acked-by: Suanming Mou --- doc/guides/nics/mlx5.rst | 3 +++ drivers/net/mlx5/linux/mlx5_os.c | 16 ++++++++++++++++ drivers/net/mlx5/mlx5_flow.c | 4 ++++ 3 files changed, 23 insertions(+) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 6510e74fb9..350fb0287e 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -1137,6 +1137,9 @@ for an additional list of options shared with other mlx5 drivers. - 0. If representor matching is disabled, then there will be no implicit item added. As a result, ingress flow rules will match traffic coming to any port, not only the port on which flow rule is created. + Because of that, default flow rules for ingress traffic cannot be created + and port starts in isolated mode by default. Port cannot be switched back + to non-isolated mode. - 1. If representor matching is enabled (default setting), then each ingress pattern template has an implicit REPRESENTED_PORT diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index a71474c90a..2cce0a7f0f 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1613,6 +1613,22 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, err = EINVAL; goto error; } + /* + * If representor matching is disabled, PMD cannot create default flow rules + * to receive traffic for all ports, since implicit source port match is not added. + * Isolated mode is forced. + */ + if (priv->sh->config.dv_esw_en && !priv->sh->config.repr_matching) { + err = mlx5_flow_isolate(eth_dev, 1, NULL); + if (err < 0) { + err = -err; + goto error; + } + DRV_LOG(WARNING, "port %u ingress traffic is restricted to defined " + "flow rules (isolated mode) since representor " + "matching is disabled", + eth_dev->data->port_id); + } return eth_dev; #else DRV_LOG(ERR, "DV support is missing for HWS."); diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index a6a426caf7..7ee30bdd1f 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -8077,6 +8077,10 @@ mlx5_flow_isolate(struct rte_eth_dev *dev, "port must be stopped first"); return -rte_errno; } + if (!enable && !priv->sh->config.repr_matching) + return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, + "isolated mode cannot be disabled when " + "representor matching is disabled"); priv->isolated = !!enable; if (enable) dev->dev_ops = &mlx5_dev_ops_isolate;