From patchwork Tue May 30 09:12:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Sekhar T K X-Patchwork-Id: 127699 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ADB0842BE1; Tue, 30 May 2023 11:13:02 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8446040F18; Tue, 30 May 2023 11:13:02 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A646D40A82 for ; Tue, 30 May 2023 11:13:00 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34U7dacm000485 for ; Tue, 30 May 2023 02:12:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=coaifsp+RZUpvkucF4Zu8MZlEK3mF+I8SdJPOG4TqZk=; b=ORt7aj9Bs5DrlgI48WCarpx0Qr5vxSRkmodnQOk2wLD0FH4YDYdBex2YXZZC4u7SI4h5 wQoI0taSj9UaJ81k2igjUh+hMJkh2cS9sXa337QA0voy9sXgQIWftGasD6xdc6sIF/DW CFx2OUxE1kuIiAhveZPsEn5ZB9apLTHXhS0idrgYmap+k/ZJthoLDczvjoKa7idsVUax N7A2jahSXf7y/zJ/A1zg6jLzMQ8XkwpGDViKIWzHhIIAQl3iV3F0JUo/+V/Uk4bBDLyl kjXT/Pth5a68xwY7qgt+k1HP9sw6YrQ2HzlUiHmNspfjA1FoqS3DsV2da6MdVYI0zU2C 0w== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3quf7phcfw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 30 May 2023 02:12:59 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 30 May 2023 02:12:57 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 30 May 2023 02:12:57 -0700 Received: from localhost.localdomain (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id 536813F7043; Tue, 30 May 2023 02:12:54 -0700 (PDT) From: Ashwin Sekhar T K To: , Nithin Kumar Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao CC: , , , , , , Subject: [PATCH v3] common/cnxk: add new APIs for batch operations Date: Tue, 30 May 2023 14:42:51 +0530 Message-ID: <20230530091251.1040406-1-asekhar@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230526134507.885354-1-asekhar@marvell.com> References: <20230526134507.885354-1-asekhar@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: NNAPREv558IlULJy9J_H4CG-A7-JR4d6 X-Proofpoint-ORIG-GUID: NNAPREv558IlULJy9J_H4CG-A7-JR4d6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-30_06,2023-05-29_02,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add new APIs for counting and extracting allocated objects from a single cache line in the batch alloc memory. Signed-off-by: Ashwin Sekhar T K --- drivers/common/cnxk/roc_npa.h | 78 ++++++++++++++++++++++++++++++----- 1 file changed, 67 insertions(+), 11 deletions(-) diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index e1e164499e..4ad5f044b5 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -209,7 +209,6 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, uint64_t *buf, unsigned int num, const int dis_wait, const int drop) { - unsigned int i; int64_t *addr; uint64_t res; union { @@ -220,10 +219,6 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, uint64_t *buf, if (num > ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS) return -1; - /* Zero first word of every cache line */ - for (i = 0; i < num; i += (ROC_ALIGN / sizeof(uint64_t))) - buf[i] = 0; - addr = (int64_t *)(roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_BATCH_ALLOC); cmp.u = 0; @@ -240,6 +235,9 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, uint64_t *buf, return 0; } +/* + * Wait for a batch alloc operation on a cache line to complete. + */ static inline void roc_npa_batch_alloc_wait(uint64_t *cache_line, unsigned int wait_us) { @@ -255,6 +253,23 @@ roc_npa_batch_alloc_wait(uint64_t *cache_line, unsigned int wait_us) break; } +/* + * Count the number of pointers in a single batch alloc cache line. + */ +static inline unsigned int +roc_npa_aura_batch_alloc_count_line(uint64_t *line, unsigned int wait_us) +{ + struct npa_batch_alloc_status_s *status; + + status = (struct npa_batch_alloc_status_s *)line; + roc_npa_batch_alloc_wait(line, wait_us); + + return status->count; +} + +/* + * Count the number of pointers in a sequence of batch alloc cache lines. + */ static inline unsigned int roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf, unsigned int num, unsigned int wait_us) @@ -279,6 +294,40 @@ roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf, unsigned int num, return count; } +/* + * Extract allocated pointers from a single batch alloc cache line. This api + * only extracts the required number of pointers from the cache line and it + * adjusts the statsus->count so that a subsequent call to this api can + * extract the remaining pointers in the cache line appropriately. + */ +static inline unsigned int +roc_npa_aura_batch_alloc_extract_line(uint64_t *buf, uint64_t *line, + unsigned int num, unsigned int *rem) +{ + struct npa_batch_alloc_status_s *status; + unsigned int avail; + + status = (struct npa_batch_alloc_status_s *)line; + roc_npa_batch_alloc_wait(line, 0); + avail = status->count; + num = avail > num ? num : avail; + if (num) + memcpy(buf, &line[avail - num], num * sizeof(uint64_t)); + avail -= num; + if (avail == 0) { + /* Clear the lowest 7 bits of the first pointer */ + buf[0] &= ~0x7FUL; + status->ccode = 0; + } + status->count = avail; + *rem = avail; + + return num; +} + +/* + * Extract all allocated pointers from a sequence of batch alloc cache lines. + */ static inline unsigned int roc_npa_aura_batch_alloc_extract(uint64_t *buf, uint64_t *aligned_buf, unsigned int num) @@ -330,11 +379,15 @@ roc_npa_aura_op_bulk_free(uint64_t aura_handle, uint64_t const *buf, } } +/* + * Issue a batch alloc operation on a sequence of cache lines, wait for the + * batch alloc to complete and copy the pointers out into the user buffer. + */ static inline unsigned int roc_npa_aura_op_batch_alloc(uint64_t aura_handle, uint64_t *buf, - uint64_t *aligned_buf, unsigned int num, - const int dis_wait, const int drop, - const int partial) + unsigned int num, uint64_t *aligned_buf, + unsigned int aligned_buf_sz, const int dis_wait, + const int drop, const int partial) { unsigned int count, chunk, num_alloc; @@ -344,9 +397,12 @@ roc_npa_aura_op_batch_alloc(uint64_t aura_handle, uint64_t *buf, count = 0; while (num) { - chunk = (num > ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS) ? - ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS : - num; + /* Make sure that the pointers allocated fit into the cache + * lines reserved. + */ + chunk = aligned_buf_sz / sizeof(uint64_t); + chunk = PLT_MIN(num, chunk); + chunk = PLT_MIN((int)chunk, ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS); if (roc_npa_aura_batch_alloc_issue(aura_handle, aligned_buf, chunk, dis_wait, drop))