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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT053.mail.protection.outlook.com (10.13.177.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6500.21 via Frontend Transport; Mon, 12 Jun 2023 08:04:40 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Mon, 12 Jun 2023 01:04:25 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Mon, 12 Jun 2023 01:04:23 -0700 From: Rongwei Liu To: , , , , , Subject: [PATCH v1] net/mlx5: adapt parse graph header length limitation Date: Mon, 12 Jun 2023 11:04:08 +0300 Message-ID: <20230612080408.2029533-1-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT053:EE_|CYYPR12MB8939:EE_ X-MS-Office365-Filtering-Correlation-Id: b742e260-3f92-4f30-93ba-08db6b1bac5f X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jun 2023 08:04:40.1259 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b742e260-3f92-4f30-93ba-08db6b1bac5f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8939 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Firmware exports the parse graph header length capability via hca_attr and the current value is 6. The user must specify the header length field via field_size. Field size implies the mask implicitly as 2^field_size-1 1. If field_size is bigger than 6, PMD needs to add an extra offset internally, let HW only parses the 6 LSBs as length. length |--------|--------|--------|--------| The actual header length offset 8 doesn't work well with new firmware, only the bits 8-13 are read and parsed as a length field. Need to change the offset to 10 (8 + 2) internally. Field mask can't be bigger than 0x3F (2^6-1). 2. If filed_size is smaller that 6, PMD needs to subtract an offset to fit 6 bits exactly. length |--------|----|------------|--------| The actual header length offset 8 doesn't work well with new firmware because firmware will read two more bits from the next field. Need to change the offset to 6 (8 -2) internally. Signed-off-by: Rongwei Liu Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5.c | 3 +++ drivers/net/mlx5/mlx5_flow_flex.c | 22 +++++++++++++++++++++- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index a75fa1b7f0..f9aea13187 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1057,6 +1057,7 @@ mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev) uint32_t ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; struct mlx5_priv *priv = dev->data->dev_private; struct mlx5_common_dev_config *config = &priv->sh->cdev->config; + struct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex; void *fp = NULL, *ibv_ctx = priv->sh->cdev->ctx; int ret; @@ -1079,6 +1080,8 @@ mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev) node.header_length_field_shift = 0x3; /* Header length is the 2nd byte. */ node.header_length_field_offset = 0x8; + if (attr->header_length_mask_width < 8) + node.header_length_field_offset += 8 - attr->header_length_mask_width; node.header_length_field_mask = 0xF; /* One byte next header protocol. */ node.next_header_field_size = 0x8; diff --git a/drivers/net/mlx5/mlx5_flow_flex.c b/drivers/net/mlx5/mlx5_flow_flex.c index 4f66b7dd1a..4ae03a23f1 100644 --- a/drivers/net/mlx5/mlx5_flow_flex.c +++ b/drivers/net/mlx5/mlx5_flow_flex.c @@ -484,6 +484,14 @@ mlx5_flex_translate_length(struct mlx5_hca_flex_attr *attr, return rte_flow_error_set (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, "unsupported header length field mode (OFFSET)"); + if (!field->field_size) + return rte_flow_error_set + (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "field size is a must for offset mode"); + if (field->field_size + field->offset_base < attr->header_length_mask_width) + return rte_flow_error_set + (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "field size plus offset_base is too small"); node->header_length_mode = MLX5_GRAPH_NODE_LEN_FIELD; if (field->offset_mask == 0 || !rte_is_power_of_2(field->offset_mask + 1)) @@ -539,9 +547,21 @@ mlx5_flex_translate_length(struct mlx5_hca_flex_attr *attr, return rte_flow_error_set (error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, NULL, "header length field shift exceeds limit"); - node->header_length_field_shift = field->offset_shift; + node->header_length_field_shift = field->offset_shift; node->header_length_field_offset = field->offset_base; } + if (field->field_mode == FIELD_MODE_OFFSET) { + if (field->field_size > attr->header_length_mask_width) { + node->header_length_field_offset += + field->field_size - attr->header_length_mask_width; + } else if (field->field_size < attr->header_length_mask_width) { + node->header_length_field_offset -= + attr->header_length_mask_width - field->field_size; + node->header_length_field_mask = + RTE_MIN(node->header_length_field_mask, + (1u << field->field_size) - 1); + } + } return 0; }