From patchwork Fri Aug 25 03:57:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Sekhar T K X-Patchwork-Id: 130733 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BC7EB430FB; Fri, 25 Aug 2023 05:57:32 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A68DD40A7A; Fri, 25 Aug 2023 05:57:32 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 5AD8340695 for ; Fri, 25 Aug 2023 05:57:31 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37P3YEr9025590 for ; Thu, 24 Aug 2023 20:57:30 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=2eXa894E67Q3W8/x3tYgnEYXyP0dmcMaFaZVw7s48k0=; b=TiAbGZ1nA8DCuXaqFvMj6Y1bWLjwAAwqnaf1mzFqEQFQ88s6nTjrnaUbVtKoDLw3dR5P RXvy0x471nCyvKwwqRQrzmvSJWiR1gKyibDifFLVpof6SozD+XbHWFPxzEdO7/odC3F8 NPzQWIQACZeSz9XwRuq8WwJDyjewRkn1wTqR/XQyJXmkGMa1jpKbevLnq7zN43vmrwN9 CdFfJprOURfxglJUIeYmt9igoTYFug/AuIlaoiZmEh5mC1tLGAJhMswHOfEgUeMW5Moo 5CkhoFvr23VG4i5aJpLbBAbsQmnCvMS+T1dy3inzs7DrafZChqkQpOJv1sRDOXI5/Rxr zQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3spmgvr1sq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 24 Aug 2023 20:57:30 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 24 Aug 2023 20:57:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 24 Aug 2023 20:57:28 -0700 Received: from localhost.localdomain (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id 7FC4D3F7093; Thu, 24 Aug 2023 20:57:24 -0700 (PDT) From: Ashwin Sekhar T K To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , , , , , , Subject: [PATCH v2] common/cnxk: fix bp_ena clear while disabling aura Date: Fri, 25 Aug 2023 09:27:21 +0530 Message-ID: <20230825035721.2723124-1-asekhar@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230822173041.2638567-1-asekhar@marvell.com> References: <20230822173041.2638567-1-asekhar@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: pknLH0Q8nk57bYdomjy8LsICB9_YB8gJ X-Proofpoint-ORIG-GUID: pknLH0Q8nk57bYdomjy8LsICB9_YB8gJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-25_01,2023-08-24_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org As done in FLR, similar to CQ disable, in process of aura disable we need to explicitly clear BP_ENA in order to deassert backpressure if it was earlier asserted. Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations") Signed-off-by: Nithin Dabilpuram Signed-off-by: Ashwin Sekhar T K --- drivers/common/cnxk/roc_npa.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index 3b9a70028b..20801739dc 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -185,6 +185,8 @@ npa_aura_pool_fini(struct mbox *m_box, uint32_t aura_id, uint64_t aura_handle) aura_req->op = NPA_AQ_INSTOP_WRITE; aura_req->aura.ena = 0; aura_req->aura_mask.ena = ~aura_req->aura_mask.ena; + aura_req->aura.bp_ena = 0; + aura_req->aura_mask.bp_ena = ~aura_req->aura_mask.bp_ena; rc = mbox_process(mbox); if (rc < 0)