From patchwork Mon Oct 30 21:12:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sevincer, Abdullah" X-Patchwork-Id: 133631 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BD66443247; Mon, 30 Oct 2023 22:12:51 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5CC7A40266; Mon, 30 Oct 2023 22:12:51 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 1C51540042; Mon, 30 Oct 2023 22:12:48 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698700369; x=1730236369; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QUgpOF9kbEL7HJlJpZKFk5SDDcHJTaIfnK7ZIyIokCk=; b=Iq9fLUJtkss+EEI8tEcBVYr25Yn7qxj4QysrKK5amrl3deBY2xysqNtz Wo44vfE2/NQ6xPffKARyPdIHVLq8/vvrb2mcTTYIH9TisdtldHdTKq7UH IdgzADeg5RsGpyn7t/2L+0TzsfpXPKSTLyVWJ4WXU7QSq3QBkAqKa4oAa 43P52gb3A58kq9JTgndf1VBKEXa/YmXlUpo2a3zVKcZS/ccF4oBl3s2Et 7qqOX1fJPpwkfY5vswLKgMhwUyBNVvK9KVCv46AbT2Yo6A68i7P4jbacO aQKOOUmmYwXWdSg/f7Ff8oaJBq/XA6/0oNv909gjsZ9RpIu91xp6YpkJN g==; X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="368372333" X-IronPort-AV: E=Sophos;i="6.03,264,1694761200"; d="scan'208";a="368372333" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2023 14:12:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10879"; a="884004404" X-IronPort-AV: E=Sophos;i="6.03,264,1694761200"; d="scan'208";a="884004404" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by orsmga004.jf.intel.com with ESMTP; 30 Oct 2023 14:12:46 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, mike.ximing.chen@intel.com, bruce.richardson@intel.com, Abdullah Sevincer , stable@dpdk.org Subject: [PATCH v3] event/dlb2: fix disable PASID for kernel 6.2 Date: Mon, 30 Oct 2023 16:12:44 -0500 Message-Id: <20231030211244.2516043-1-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607210050.107944-1-abdullah.sevincer@intel.com> References: <20230607210050.107944-1-abdullah.sevincer@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org vfio-pci driver in Linux kernel 6.2 enables PASID by default. In DLB hardware, enabling PASID puts DLB in SIOV mode. This breaks DLB PF-PMD mode. For DLB PF-PMD mode to function properly PASID needs to be disabled for kernel 6.2. In this commit this issue is addressed and PASID is disabled by writing a zero to PASID control register. Fixes: 5433956d5185 ("event/dlb2: add eventdev probe") Cc: stable@dpdk.org Signed-off-by: Abdullah Sevincer --- drivers/event/dlb2/pf/dlb2_main.c | 27 +++++++++++++++++++++++++++ lib/pci/rte_pci.h | 5 +++++ 2 files changed, 32 insertions(+) diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c index aa03e4c311..34e47a4e33 100644 --- a/drivers/event/dlb2/pf/dlb2_main.c +++ b/drivers/event/dlb2/pf/dlb2_main.c @@ -190,6 +190,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) uint16_t rt_ctl_word; uint32_t pri_reqs_dword; uint16_t pri_ctrl_word; + uint16_t pasid_ctrl; off_t pcie_cap_offset; int pri_cap_offset; @@ -197,6 +198,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) int err_cap_offset; int acs_cap_offset; int wait_count; + int pasid_cap_offset; uint16_t devsta_busy_word; uint16_t devctl_word; @@ -514,6 +516,31 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev) } } + /* TODO - The current Linux kernel 6.2 vfio driver does not expose PASID capability to + * users. It also enables PASID by default, which breaks DLB PF PMD. We have + * to use the hardcoded offset for now to disable PASID. It may be different for + * other device drivers since they may have different design. When PASID capability + * is exposed to users, please revise this part and add api to disable PASID through + * pci common code. + */ + pasid_cap_offset = RTE_PCI_PASID_CAP_OFFSET; + + off = pasid_cap_offset + RTE_PCI_PASID_CTRL; + if (rte_pci_read_config(pdev, &pasid_ctrl, 2, off) != 2) + pasid_ctrl = 0; + + if (pasid_ctrl) { + DLB2_INFO(dlb2_dev, "DLB2 disabling pasid...\n"); + + pasid_ctrl = 0; + ret = rte_pci_write_config(pdev, &pasid_ctrl, 2, off); + if (ret != 2) { + DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n", + __func__, (int)off); + return ret; + } + } + return 0; } diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index 69e932d910..772a8d5622 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -101,6 +101,11 @@ extern "C" { #define RTE_PCI_EXT_CAP_ID_ACS 0x0d /* Access Control Services */ #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV */ #define RTE_PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ +#define RTE_PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ + +/* Process Address Space ID */ +#define RTE_PCI_PASID_CTRL 0x06 /* PASID control register */ +#define RTE_PCI_PASID_CAP_OFFSET 0x148 /* PASID capability offset */ /* Advanced Error Reporting (RTE_PCI_EXT_CAP_ID_ERR) */ #define RTE_PCI_ERR_UNCOR_STATUS 0x04 /* Uncorrectable Error Status */