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Thu, 30 Nov 2023 08:40:08 -0800 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou , Erez Shitrit Subject: [PATCH v2 1/2] net/mlx5/hws: add support for random number match Date: Thu, 30 Nov 2023 18:40:00 +0200 Message-ID: <20231130164001.666702-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231130164001.666702-1-michaelba@nvidia.com> References: <20230822103600.3247680-1-michaelba@nvidia.com> <20231130164001.666702-1-michaelba@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E8:EE_|PH0PR12MB7011:EE_ X-MS-Office365-Filtering-Correlation-Id: f1b240e2-f9c0-4930-2312-08dbf1c30ec2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RF2q/Upf3Yfv2oHYbVQg4XnSXeSVHYrw6o+r52tGsnvf44n45kXbT8cdjKSkgWoPzj6s2xSwPhVctjn/ImDG4TZxEONHbBw/89IhiLUervgoX2e6nv42+QOxXVuO6fC5hEO71OexhH5AtHE5xg1YUGvyZiBYNGKPk4u/LUjMvTCfTWoA6TnsVOu57RvtM0sxIawdxey5yKSV2KJxVCluC0I2+IymWhI76hGuxgaKZVcW4dBAKuiMOCqmqDA+F9JfaVprCGs61TKPvTzjm4ugPmDb2c1/3juIwAF8Y5qUhXbin6wJsoTEcEh9TxWBFIm97fzmCtiITj4aIZTbiwbi5Im4WHqKwgxeXBIKG8R+yQldJtjEsvxhNAdOs++AIOqZUCzdhLM3GVi4dddXF1lARzhXkSt1Qbt/zOIOnB/6OXuPddj0htbwRrgHQ3rW6tA7TtSKMTsGgO+MCkeLM7uTXCKUhfFxySDKOpgHvol+CWwOK+LCTcdHWI0ZHCGhmA2cmLavT8K8RB44FvaE8/SCReLPfOAeT6HX+u5R6MfEB44IUuqa9hrDfHvIS0PR9vHEZLxP3ziXltkTQXySidGpFPi+w7Fc+V6Muf+deMlN7Jm5HNLzLqanrT35teW+vJdIigdTiwq7oxXv3f01w08IB4CrknQHmiCbXXaz/PbyYSXtVMsIgGAxUMA4qI/nrjEzVD7taxTSStO5Fk6vKzjAgaWqcESrrdNov5Wj5+PLVVye44SWyPLS0Eda3z1spIL5 X-Forefront-Antispam-Report: CIP:216.228.117.161; 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Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7011 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Erez Shitrit The HW adds a random number per each hash, this value can be used for statistic calculation over the packets, for example by setting one bit in the mask of that filed we will get half of the traffic in the flow, and so on with the rest of the mask. Signed-off-by: Erez Shitrit --- drivers/net/mlx5/hws/mlx5dr_definer.c | 33 +++++++++++++++++++++++++++ drivers/net/mlx5/hws/mlx5dr_definer.h | 8 ++++++- drivers/net/mlx5/mlx5_flow.h | 3 +++ 3 files changed, 43 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 0b60479406..005733372a 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -182,6 +182,7 @@ struct mlx5dr_definer_conv_data { X(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp) \ X(SET, ib_l4_udp_port, UDP_ROCEV2_PORT, rte_flow_item_ib_bth) \ X(SET, ib_l4_opcode, v->hdr.opcode, rte_flow_item_ib_bth) \ + X(SET, random_number, v->value, rte_flow_item_random) \ X(SET, ib_l4_bth_a, v->hdr.a, rte_flow_item_ib_bth) \ /* Item set function format */ @@ -2173,6 +2174,33 @@ mlx5dr_definer_conv_item_ipv6_routing_ext(struct mlx5dr_definer_conv_data *cd, return 0; } +static int +mlx5dr_definer_conv_item_random(struct mlx5dr_definer_conv_data *cd, + struct rte_flow_item *item, + int item_idx) +{ + const struct rte_flow_item_random *m = item->mask; + const struct rte_flow_item_random *l = item->last; + struct mlx5dr_definer_fc *fc; + + if (!m) + return 0; + + if (m->value != (m->value & UINT16_MAX)) { + DR_LOG(ERR, "Random value is 16 bits only"); + rte_errno = EINVAL; + return rte_errno; + } + + fc = &cd->fc[MLX5DR_DEFINER_FNAME_RANDOM_NUM]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_random_number_set; + fc->is_range = l && l->value; + DR_CALC_SET_HDR(fc, random_number, random_number); + + return 0; +} + static int mlx5dr_definer_mt_set_fc(struct mlx5dr_match_template *mt, struct mlx5dr_definer_fc *fc, @@ -2224,6 +2252,7 @@ mlx5dr_definer_check_item_range_supp(struct rte_flow_item *item) case RTE_FLOW_ITEM_TYPE_TAG: case RTE_FLOW_ITEM_TYPE_META: case MLX5_RTE_FLOW_ITEM_TYPE_TAG: + case RTE_FLOW_ITEM_TYPE_RANDOM: return 0; default: DR_LOG(ERR, "Range not supported over item type %d", item->type); @@ -2537,6 +2566,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx, ret = mlx5dr_definer_conv_item_ptype(&cd, items, i); item_flags |= MLX5_FLOW_ITEM_PTYPE; break; + case RTE_FLOW_ITEM_TYPE_RANDOM: + ret = mlx5dr_definer_conv_item_random(&cd, items, i); + item_flags |= MLX5_FLOW_ITEM_RANDOM; + break; default: DR_LOG(ERR, "Unsupported item type %d", items->type); rte_errno = ENOTSUP; diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index 6f1c99e37a..18591ef853 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -150,6 +150,7 @@ enum mlx5dr_definer_fname { MLX5DR_DEFINER_FNAME_PTYPE_TUNNEL, MLX5DR_DEFINER_FNAME_PTYPE_FRAG_O, MLX5DR_DEFINER_FNAME_PTYPE_FRAG_I, + MLX5DR_DEFINER_FNAME_RANDOM_NUM, MLX5DR_DEFINER_FNAME_MAX, }; @@ -407,6 +408,11 @@ struct mlx5_ifc_definer_hl_ipv4_src_dst_bits { u8 destination_address[0x20]; }; +struct mlx5_ifc_definer_hl_random_number_bits { + u8 random_number[0x10]; + u8 reserved[0x10]; +}; + struct mlx5_ifc_definer_hl_ipv6_addr_bits { u8 ipv6_address_127_96[0x20]; u8 ipv6_address_95_64[0x20]; @@ -516,7 +522,7 @@ struct mlx5_ifc_definer_hl_bits { struct mlx5_ifc_definer_hl_mpls_bits mpls_inner; u8 unsupported_config_headers_outer[0x80]; u8 unsupported_config_headers_inner[0x80]; - u8 unsupported_random_number[0x20]; + struct mlx5_ifc_definer_hl_random_number_bits random_number; struct mlx5_ifc_definer_hl_ipsec_bits ipsec; struct mlx5_ifc_definer_hl_metadata_bits metadata; u8 unsupported_utc_timestamp[0x40]; diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 6dde9de688..14311eff10 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -277,6 +277,9 @@ enum mlx5_feature_name { /* NSH ITEM */ #define MLX5_FLOW_ITEM_NSH (1ull << 53) +/* Random ITEM */ +#define MLX5_FLOW_ITEM_RANDOM (1ull << 53) + /* Outer Masks. */ #define MLX5_FLOW_LAYER_OUTER_L3 \ (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6) From patchwork Thu Nov 30 16:40:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Baum X-Patchwork-Id: 134738 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B412343412; 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Signed-off-by: Michael Baum --- doc/guides/nics/features/mlx5.ini | 1 + doc/guides/nics/mlx5.rst | 10 +++++++++- doc/guides/rel_notes/release_24_03.rst | 3 +++ drivers/net/mlx5/mlx5_flow_dv.c | 5 +++++ drivers/net/mlx5/mlx5_flow_hw.c | 5 +++++ 5 files changed, 23 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/features/mlx5.ini b/doc/guides/nics/features/mlx5.ini index 0739fe9d63..6261b7d657 100644 --- a/doc/guides/nics/features/mlx5.ini +++ b/doc/guides/nics/features/mlx5.ini @@ -88,6 +88,7 @@ port_id = Y port_representor = Y ptype = Y quota = Y +random = Y tag = Y tcp = Y udp = Y diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 6b52fb93c5..129f7d9d24 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -167,7 +167,7 @@ Features - Sub-Function. - Matching on represented port. - Matching on aggregated affinity. - +- Matching on random value. Limitations ----------- @@ -564,6 +564,7 @@ Limitations - Modification of the MPLS header is supported only in HWS and only to copy from, the encapsulation level is always 0. - Modification of the 802.1Q Tag, VXLAN Network or GENEVE Network ID's is not supported. + - Modify field action using ``RTE_FLOW_FIELD_RANDOM`` is not supported. - Encapsulation levels are not supported, can modify outermost header fields only. - Offsets cannot skip past the boundary of a field. - If the field type is ``RTE_FLOW_FIELD_MAC_TYPE`` @@ -770,6 +771,13 @@ Limitations - In HW steering (``dv_flow_en`` = 2): - not supported on guest port. +- Match on random value: + + - Supported only with HW Steering enabled (``dv_flow_en`` = 2). + - Supported only in table with ``nb_flows=1``. + - NIC ingress flow in group 0 is not supported. + - Supports matching only 16 bits (LSB). + - During live migration to a new process set its flow engine as standby mode, the user should only program flow rules in group 0 (``fdb_def_rule_en=0``). Live migration is only supported under SWS (``dv_flow_en=1``). diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst index ab91ce2b21..164cf74f5b 100644 --- a/doc/guides/rel_notes/release_24_03.rst +++ b/doc/guides/rel_notes/release_24_03.rst @@ -59,6 +59,9 @@ New Features Added ``RTE_FLOW_ITEM_RANDOM`` to match random value. +* **Updated NVIDIA mlx5 net driver.** + + * Added support for ``RTE_FLOW_ITEM_TYPE_RUNDOM`` flow item. Removed Items ------------- diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 115d730317..67a44095d7 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -5396,6 +5396,11 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, RTE_FLOW_ERROR_TYPE_ACTION, action, "modifications of the MPLS header " "is not supported"); + if (dst_data->field == RTE_FLOW_FIELD_RANDOM || + src_data->field == RTE_FLOW_FIELD_RANDOM) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "modifications of random value is not supported"); if (dst_data->field == RTE_FLOW_FIELD_MARK || src_data->field == RTE_FLOW_FIELD_MARK) if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index da873ae2e2..af4e9abd89 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -5047,6 +5047,10 @@ flow_hw_validate_action_modify_field(struct rte_eth_dev *dev, return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, "modifying vlan_type is not supported"); + if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_RANDOM)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "modifying random value is not supported"); if (flow_hw_modify_field_is_used(action_conf, RTE_FLOW_FIELD_GENEVE_VNI)) return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, action, @@ -6807,6 +6811,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev, case RTE_FLOW_ITEM_TYPE_FLEX: case RTE_FLOW_ITEM_TYPE_IB_BTH: case RTE_FLOW_ITEM_TYPE_PTYPE: + case RTE_FLOW_ITEM_TYPE_RANDOM: break; case RTE_FLOW_ITEM_TYPE_INTEGRITY: /*