From patchwork Mon Dec 18 13:41:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arkadiusz Kusztal X-Patchwork-Id: 135279 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9FCB043735; Mon, 18 Dec 2023 15:53:31 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6E7C441140; Mon, 18 Dec 2023 15:53:31 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by mails.dpdk.org (Postfix) with ESMTP id 6477041132 for ; Mon, 18 Dec 2023 15:53:29 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702911209; x=1734447209; h=from:to:cc:subject:date:message-id; bh=wFjlQPbYROahJEMhZ/LTWkNgI8k9nEyyfgiMBZJ6v4o=; b=iB8zZUQHYZs02fUJ+XGUlmZ8qrWjAKBiKDm+E6T+Ieq0UyXiPgn6ICkC xjHTiINwzvL8NRXxGutzl46xt6oCS6IDbcycXkLckgFIrcSm9xcKLdFw2 PEUNkVdpaK7UcmRoKQsexNAgJiMWJNGThtdqNnAl/FbdwQhdWs0lmU7cb I307yTVg054qezRXalHL4TEoo/QXUcrV8exCH0pC8lQXFZvbH0WZ1rNFN lHrNa1BEJiNKj+L0XgLBlDTt7A/JcFfl3J/jkH+j2/lbCWyZKNNldaIyr AmXi+Mky4LFc9WR/WASbLiKn/HMD1yFMki9UwqmndrV8fkpRzY0GB/jTp g==; X-IronPort-AV: E=McAfee;i="6600,9927,10928"; a="2725509" X-IronPort-AV: E=Sophos;i="6.04,285,1695711600"; d="scan'208";a="2725509" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Dec 2023 06:53:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10928"; a="1022776792" X-IronPort-AV: E=Sophos;i="6.04,285,1695711600"; d="scan'208";a="1022776792" Received: from silpixa00399302.ir.intel.com ([10.237.214.136]) by fmsmga006.fm.intel.com with ESMTP; 18 Dec 2023 06:53:26 -0800 From: Arkadiusz Kusztal To: dev@dpdk.org Cc: gakhil@marvell.com, kai.ji@intel.com, ciara.power@intel.com, Arkadiusz Kusztal Subject: [PATCH 1/2] common/qat: add vqat definition to pmd map Date: Mon, 18 Dec 2023 13:41:41 +0000 Message-Id: <20231218134142.84397-1-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.13.6 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit adds vqat (virtual QAT device) to PMD PCI ID map. Signed-off-by: Arkadiusz Kusztal --- drivers/common/qat/qat_common.h | 1 + drivers/common/qat/qat_device.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h index 9411a79301..53799ce174 100644 --- a/drivers/common/qat/qat_common.h +++ b/drivers/common/qat/qat_common.h @@ -21,6 +21,7 @@ enum qat_device_gen { QAT_GEN2, QAT_GEN3, QAT_GEN4, + QAT_VQAT, QAT_N_GENS }; diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c index f55dc3c6f0..5e00c200a6 100644 --- a/drivers/common/qat/qat_device.c +++ b/drivers/common/qat/qat_device.c @@ -199,6 +199,8 @@ pick_gen(const struct rte_pci_device *pci_dev) case 0x4943: case 0x4945: return QAT_GEN4; + case 0x0da5: + return QAT_VQAT; default: QAT_LOG(ERR, "Invalid dev_id, can't determine generation"); return QAT_N_GENS; From patchwork Mon Dec 18 13:41:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arkadiusz Kusztal X-Patchwork-Id: 135280 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 45D0343735; Mon, 18 Dec 2023 15:53:37 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 902A4427DF; Mon, 18 Dec 2023 15:53:33 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) by mails.dpdk.org (Postfix) with ESMTP id 1AC6C427DC for ; Mon, 18 Dec 2023 15:53:31 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702911212; x=1734447212; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=ZM9ySOjjEXYKdSWCoWoDb/z6eTAe6i2lWnXjh1qr0JM=; b=BaCKjqh/9k0RLYM3HQLzAsq8haJs7zAkv+HyFeEWovrJ5O89BdCqRQVA Fh/nfzSFOHp/S5dZfGb0stVktBP9gOUN4NdpfCjJ1L8mjvdHqFyBeazJj TN742rhPjV6utkQO1Zy6KqeAQhI+xCVA70vVzaNQpOeOLy7YyUgTdLdM1 rAQkmFQEyo4y2+vXRZCzVJHknqvWgcRCQSSpggd2SSOfDFb1//EzTAGkg W1mlezvsFQaSX5dt/BxxnU22vbPznMkRrVZkuVc8dZFK8BMY9h1+a2R70 P0xVPWRnOoTMv3mAD28j3r1pFJvH1Zmx6MJn5Y45eVv8xp8rEOgjsym+9 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10928"; a="2725517" X-IronPort-AV: E=Sophos;i="6.04,285,1695711600"; d="scan'208";a="2725517" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Dec 2023 06:53:31 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10928"; a="1022776803" X-IronPort-AV: E=Sophos;i="6.04,285,1695711600"; d="scan'208";a="1022776803" Received: from silpixa00399302.ir.intel.com ([10.237.214.136]) by fmsmga006.fm.intel.com with ESMTP; 18 Dec 2023 06:53:29 -0800 From: Arkadiusz Kusztal To: dev@dpdk.org Cc: gakhil@marvell.com, kai.ji@intel.com, ciara.power@intel.com, Arkadiusz Kusztal Subject: [PATCH 2/2] common/qat: add vqat confiuration macros Date: Mon, 18 Dec 2023 13:41:42 +0000 Message-Id: <20231218134142.84397-2-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20231218134142.84397-1-arkadiuszx.kusztal@intel.com> References: <20231218134142.84397-1-arkadiuszx.kusztal@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit adds vqat (virtual QAT device) configuration macros to the Intel QuickAssist Technology PMD. Signed-off-by: Arkadiusz Kusztal --- .../qat/qat_adf/adf_transport_access_macros_vqat.h | 82 ++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 drivers/common/qat/qat_adf/adf_transport_access_macros_vqat.h diff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros_vqat.h b/drivers/common/qat/qat_adf/adf_transport_access_macros_vqat.h new file mode 100644 index 0000000000..9acf7c614d --- /dev/null +++ b/drivers/common/qat/qat_adf/adf_transport_access_macros_vqat.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) + * Copyright(c) 2023 Intel Corporation + */ + +#ifndef ADF_TRANSPORT_ACCESS_MACROS_VQAT_H +#define ADF_TRANSPORT_ACCESS_MACROS_VQAT_H + +#define ADF_RINGS_PER_INT_SRCSEL_VQAT 2 +#define ADF_BANK_INT_SRC_SEL_MASK_VQAT 0x44UL +#define ADF_BANK_INT_FLAG_CLEAR_MASK_VQAT 0x3 +#define ADF_RING_BUNDLE_SIZE_VQAT 0x2000 +#define ADF_RING_CSR_ADDR_OFFSET_VQAT 0x0 +#define ADF_RING_CSR_RING_CONFIG_VQAT ADF_VQAT_R0_CONFIG +#define ADF_RING_CSR_RING_LBASE_VQAT ADF_VQAT_R0_LBASE +#define ADF_RING_CSR_RING_UBASE_VQAT ADF_VQAT_R0_UBASE +#define ADF_RING_CSR_RP_IDX_TX 0 +#define ADF_RING_CSR_RP_IDX_RX 1 + +#define BUILD_RING_BASE_ADDR_VQAT(addr, size) \ + ((((addr) >> 6) & (0xFFFFFFFFFFFFFFFFULL << (size))) << 6) +#define READ_CSR_RING_HEAD_VQAT(csr_base_addr, bank, ring) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_RING_HEAD + ((ring) << 2)) +#define READ_CSR_RING_TAIL_VQAT(csr_base_addr, bank, ring) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_RING_TAIL + ((ring) << 2)) +#define READ_CSR_STAT_VQAT(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_STAT) +#define READ_CSR_UO_STAT_VQAT(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_UO_STAT) +#define READ_CSR_E_STAT_VQAT(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_E_STAT) +#define READ_CSR_NE_STAT_VQAT(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_NE_STAT) +#define READ_CSR_NF_STAT_VQAT(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_NF_STAT) +#define READ_CSR_F_STAT_VQAT(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_F_STAT) +#define READ_CSR_C_STAT_VQAT(csr_base_addr, bank) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_C_STAT) +#define READ_CSR_RING_CONFIG_VQAT(csr_base_addr, bank, ring) \ + ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_RING_CONFIG_VQAT + ((ring) << 2)) +#define WRITE_CSR_RING_CONFIG_VQAT(csr_base_addr, bank, ring, value) \ + ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (bank)) + \ + ADF_RING_CSR_RING_CONFIG_VQAT + ((ring) << 2), (value)) +#define WRITE_CSR_RING_BASE_VQAT(csr_base_addr, bank, ring, value) \ +do { \ + void __iomem *_csr_base_addr = csr_base_addr; \ + u32 _bank = bank; \ + u32 _ring = ring; \ + dma_addr_t _value = value; \ + u32 l_base = 0, u_base = 0; \ + l_base = (u32)((_value) & 0xFFFFFFFF); \ + u_base = (u32)(((_value) & 0xFFFFFFFF00000000ULL) >> 32); \ + ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (_bank)) + \ + ADF_RING_CSR_RING_LBASE_VQAT + ((_ring) << 2), l_base); \ + ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_VQAT, \ + (ADF_RING_BUNDLE_SIZE_VQAT * (_bank)) + \ + ADF_RING_CSR_RING_UBASE_VQAT + ((_ring) << 2), u_base); \ +} while (0) + +#endif