From patchwork Tue Mar 5 11:55:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ciara Power X-Patchwork-Id: 137992 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B939C43B6C; Tue, 5 Mar 2024 12:55:45 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 54BA040270; Tue, 5 Mar 2024 12:55:45 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by mails.dpdk.org (Postfix) with ESMTP id DC79A4026B for ; Tue, 5 Mar 2024 12:55:43 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1709639744; x=1741175744; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=cxFgZDzTVkazASJyCueLmNePDJnh9KPTKv1s1lJJKi8=; b=XOYNG4fOUwOzNTEyx0EKnszrXNg46+nHXxMu7BxxOEQPUVVAO3AIFM7H UEuEfs4s0OtwA/BJfRuOVu5mmqdDyuMhbFxtmQhj/WMxkag24+de28SKZ gEC7gx5gRJJKQNHrFtQrB6Lp+iXB/aUNQfdK5lYSRvp8WrKoDVBrF2uYr oqH0fR6c6BJ3rISTCkVqqzkey1qPN21IbLJbD2LiUwDLnedgC+dwZ6TMu W5LEiw8PDCTL3Uy7RqqLnj4WduZmGlto1HjVHO4yBJTw1pPuIjpn/G8VT fOateiPBB0o5J1CmWtplyhlKiM7oe8R9ofP7js1CNyAL4YY5x+YsHTnQ3 g==; X-IronPort-AV: E=McAfee;i="6600,9927,11003"; a="4350488" X-IronPort-AV: E=Sophos;i="6.06,205,1705392000"; d="scan'208";a="4350488" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2024 03:55:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,205,1705392000"; d="scan'208";a="13949052" Received: from silpixa00401797.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.113]) by fmviesa003.fm.intel.com with ESMTP; 05 Mar 2024 03:55:41 -0800 From: Ciara Power To: dev@dpdk.org Cc: gakhil@marvell.com, Ciara Power , nishikanta.nayak@intel.com, Kai Ji Subject: [PATCH] common/qat: fix undefined macro Date: Tue, 5 Mar 2024 11:55:36 +0000 Message-Id: <20240305115537.3042539-1-ciara.power@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When using RTE_ENABLE_ASSERT and debug mode, an undefined macro error appeared for ICP_QAT_FW_SYM_COMM_ADDR_SGL. This was not being defined, but is now added to the header file. Bugzilla ID: 1395 Fixes: e9271821e489 ("common/qat: support GEN LCE device") Signed-off-by: Ciara Power Acked-by: Nishikant Nayak Tested-by: Ali Alnubani Reported-by: Ali Alnubani --- Cc: nishikanta.nayak@intel.com --- drivers/common/qat/qat_adf/icp_qat_fw_la.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h index 67fc25c919..fe32b66c50 100644 --- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h +++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h @@ -111,6 +111,7 @@ struct icp_qat_fw_la_bulk_req { #define ICP_QAT_FW_SYM_IV_IN_DESC_VALID 1 #define ICP_QAT_FW_SYM_DIRECTION_BITPOS 15 #define ICP_QAT_FW_SYM_DIRECTION_MASK 0x1 +#define ICP_QAT_FW_SYM_COMM_ADDR_SGL 1 /* In GEN_LCE AEAD AES GCM Algorithm has ID 0 */ #define QAT_LA_CRYPTO_AEAD_AES_GCM_GEN_LCE 0