From patchwork Tue Mar 5 18:05:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dariusz Sosnowski X-Patchwork-Id: 138001 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7CD0743B76; Tue, 5 Mar 2024 19:06:40 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6946B41156; Tue, 5 Mar 2024 19:06:40 +0100 (CET) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2084.outbound.protection.outlook.com [40.107.220.84]) by mails.dpdk.org (Postfix) with ESMTP id 841D942DC3; Tue, 5 Mar 2024 19:06:38 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HFIm5U6Q7+qWpG7kKmv0cYjn570Sc1n4GxY7hJyxhcZqB9utH/2hCiEvk3e9/zFnvzFv1vWzzdGWUlxFmmsy6CjeC87xo5G4h5BPmRcQ0hrrb1i0CVKIgpssuKhqJmN04rYYUoKAVSG+JSfC4B1b6PaAzxv9yLYnOONtF66OErbkdnzNX7KtiaKP7xvAuAB2H0Je0FUTnf7LuWy80u+7gL+/nf1Orp5e+9NNHvJqmnBEji74d4j5wuL2FsiuwTTxnu2+dk6TI+HIVRSKit8raJdERU1oIjxzgiNZwnxYyjZrKDNqsygv0owBsoV4DsQOgyzcvUyNBHzWc0Fo6whv3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=bqnUYOaDG1hKmr06PaaSW++lwy4Adu8h/aGzv7VwJfs=; b=LZZOgTDPomVhpojZ/T9lm4y7CZygLx2OjifLsUx57oCm1pAgU4dWO+rH1S7OI4DgaZ00gpwKRJ03AJfFyhB1YLEfUEiSbsAAtzAHnLYAUkCl7BIGux3UjBZrFo7M2opM6i/GgXApT7UkeAqpIzCdpAezxtBGhLXWfAt8uYclalN+StLZr2R9WLoRrGrG5JrVdJ0ExF2/ll47ZneUgbBl7NXNt8LB8UFENzTisKcm7ZfDXrspkiL8/7Mkt854Dhh7XXAoGA/HV2sLzP8LQSfkoMlZxeqiKtVuyKuHV3qXDsiDrcBOJfdnMUo5OVAIjcttZelNCFWBxVsJhpEN/pHWMQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=bqnUYOaDG1hKmr06PaaSW++lwy4Adu8h/aGzv7VwJfs=; b=jmv+uOqg9ofKQZAilcF9aAK/2EwSJMg9ooS1+e0Eyxjdl0ZUJqPMkvwDTWKZo1TSPoy7LDMFbs/igacvTeGtpehiWQ2gwVxsvDNbX1Zj9qmfcTfA3+nhAXE5EZDPdACSX591DK1c7DfaMCgBSAatzn0s1Cq43QuLiiKyt4RWow/SwngI0fAWoFYYWz9S6p4I1ryqP4lpDg8Vi/4yPaMELnpYMshwK+5AbM5V80BM1SIQpDMLKQ+SO4YGBGkbDw/jmhTJWar2d5RUj5Fu20l+Pi3lMNwS99WI6rH+T7jHJ1YaDy5vWsnwqVZAjdrLW6/TDweLLHXY7Z9wzzSNuvWNaw== Received: from MN2PR20CA0047.namprd20.prod.outlook.com (2603:10b6:208:235::16) by SN7PR12MB6742.namprd12.prod.outlook.com (2603:10b6:806:26e::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.38; Tue, 5 Mar 2024 18:06:35 +0000 Received: from MN1PEPF0000ECD6.namprd02.prod.outlook.com (2603:10b6:208:235:cafe::b8) by MN2PR20CA0047.outlook.office365.com (2603:10b6:208:235::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7339.39 via Frontend Transport; Tue, 5 Mar 2024 18:06:35 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by MN1PEPF0000ECD6.mail.protection.outlook.com (10.167.242.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7362.11 via Frontend Transport; Tue, 5 Mar 2024 18:06:34 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 5 Mar 2024 10:06:05 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Tue, 5 Mar 2024 10:06:04 -0800 From: Dariusz Sosnowski To: Matan Azrad , Viacheslav Ovsiienko , Ori Kam , Suanming Mou CC: , Subject: [PATCH] net/mlx5: fix async flow create error handling Date: Tue, 5 Mar 2024 19:05:14 +0100 Message-ID: <20240305180514.50520-1-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD6:EE_|SN7PR12MB6742:EE_ X-MS-Office365-Filtering-Correlation-Id: cfb867df-3945-46e7-209f-08dc3d3efeac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: cD3TouvgscYEL9mTs4PzG9ngXaUvCpiAwHn5Kwh6tlzWubhcbePAuiSFoqmIR1Q6Tnhnm0W5lYG/vgmMZZVVH31fG6Ef9eMZzIqpXnlp0dDV53thNryLusKHVLhGrnuWZTfHcCvscMq3oJZBH/oN5DosAF4w7zCaog+FY4Jt/rkuZLYi2PIYeAf1Oz22x3lDbDIaXXzvAa8/iNqG8pg3VRT8RzJuZLDHN+7EmP2yIfrNVAFZn9JMzMI86mr6/0eO9Ah48JRTWEb9a5hWeHCXEmIt50kt1nVmKyBjpEb4KM0fxAXpkS/3g4OdO4PJQ7iXAdHxzEV/QKoyLcvWjsDulECVsvn8d1kXS5WHqNf6jLQqCDTPGE4aPt2MjT7XK+sCA1/8ne/s3mdOnUCpw2A9p6/qbQAALE/zLqLf7x9rB9CtwKEaOVTli+Oh9R4yMgzwuqW8ZorlYY+lXmQNLQTmuemt7Oz3yTbuXd20+MXh6koq76i//p/c5eEwO0XTd8oZMuyHC1rVlHp1iU04PGgCLD+gZ/28niGhJFCiGOaqzzLdSJLD+f1Ce6srjlJ1Sd5b1ZtLr/6H8Z4E4wLhJDViyWYSOhWd9bKbRGFluvZJBntyNzwvF9OcVwvlmjGucky3md/qP0YsNRutQLk+5XA8B2g4FKlM4xicCCep1HMOQSOv8OOZ/O8cZBk17oMZWX2Nrj2ePiLj8LYxKvNQPWrRMcaUl/aITQasm1/hFq4Vc/EWUF989QkodPryVMQrV6sP X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230031)(376005)(36860700004)(82310400014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Mar 2024 18:06:34.7540 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cfb867df-3945-46e7-209f-08dc3d3efeac X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD6.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6742 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Whenever processing of asynchronous flow rule create operation failed, but after some dynamic flow actions had already been allocated, these actions were not freed during error handling flow. That behavior lead to leaks e.g., RSS/QUEUE action objects were leaked which triggered assertions during device cleanup. This patch adds flow rule cleanup handling in case of an error during async flow rule creation. Fixes: 3a2f674b6aa8 ("net/mlx5: add queue and RSS HW steering action") Cc: suanmingm@nvidia.com Cc: stable@dpdk.org Signed-off-by: Dariusz Sosnowski Acked-by: Ori Kam --- drivers/net/mlx5/mlx5_flow_hw.c | 78 +++++++++++++++++++++++---------- 1 file changed, 55 insertions(+), 23 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index 4216433c6e..5a407d592c 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -174,7 +174,7 @@ mlx5_flow_hw_aux_set_mtr_id(struct rte_flow_hw *flow, aux->orig.mtr_id = mtr_id; } -static __rte_always_inline uint32_t __rte_unused +static __rte_always_inline uint32_t mlx5_flow_hw_aux_get_mtr_id(struct rte_flow_hw *flow, struct rte_flow_hw_aux *aux) { if (unlikely(flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE)) @@ -183,6 +183,10 @@ mlx5_flow_hw_aux_get_mtr_id(struct rte_flow_hw *flow, struct rte_flow_hw_aux *au return aux->orig.mtr_id; } +static void +flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue, struct rte_flow_hw *flow, + struct rte_flow_error *error); + static int mlx5_tbl_multi_pattern_process(struct rte_eth_dev *dev, struct rte_flow_template_table *tbl, @@ -3034,6 +3038,31 @@ flow_hw_modify_field_construct(struct mlx5_modification_cmd *mhdr_cmd, return 0; } +/** + * Release any actions allocated for the flow rule during actions construction. + * + * @param[in] flow + * Pointer to flow structure. + */ +static void +flow_hw_release_actions(struct rte_eth_dev *dev, + uint32_t queue, + struct rte_flow_hw *flow) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_aso_mtr_pool *pool = priv->hws_mpool; + struct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow); + + if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP) + flow_hw_jump_release(dev, flow->jump); + else if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ) + mlx5_hrxq_obj_release(dev, flow->hrxq); + if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID) + flow_hw_age_count_release(priv, queue, flow, NULL); + if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MTR_ID) + mlx5_ipool_free(pool->idx_pool, mlx5_flow_hw_aux_get_mtr_id(flow, aux)); +} + /** * Construct flow action array. * @@ -3156,7 +3185,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, (dev, queue, action, table, it_idx, at->action_flags, flow, &rule_acts[act_data->action_dst])) - return -1; + goto error; break; case RTE_FLOW_ACTION_TYPE_VOID: break; @@ -3176,7 +3205,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, jump = flow_hw_jump_action_register (dev, &table->cfg, jump_group, NULL); if (!jump) - return -1; + goto error; rule_acts[act_data->action_dst].action = (!!attr.group) ? jump->hws_action : jump->root_action; flow->jump = jump; @@ -3188,7 +3217,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, ft_flag, action); if (!hrxq) - return -1; + goto error; rule_acts[act_data->action_dst].action = hrxq->action; flow->hrxq = hrxq; flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ; @@ -3198,19 +3227,19 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, if (flow_hw_shared_action_get (dev, act_data, item_flags, &rule_acts[act_data->action_dst])) - return -1; + goto error; break; case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: enc_item = ((const struct rte_flow_action_vxlan_encap *) action->conf)->definition; if (flow_dv_convert_encap_data(enc_item, ap->encap_data, &encap_len, NULL)) - return -1; + goto error; break; case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: enc_item = ((const struct rte_flow_action_nvgre_encap *) action->conf)->definition; if (flow_dv_convert_encap_data(enc_item, ap->encap_data, &encap_len, NULL)) - return -1; + goto error; break; case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: raw_encap_data = @@ -3238,12 +3267,12 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, hw_acts, action); if (ret) - return -1; + goto error; break; case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: port_action = action->conf; if (!priv->hw_vport[port_action->port_id]) - return -1; + goto error; rule_acts[act_data->action_dst].action = priv->hw_vport[port_action->port_id]; break; @@ -3263,7 +3292,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, jump = flow_hw_jump_action_register (dev, &table->cfg, aso_mtr->fm.group, NULL); if (!jump) - return -1; + goto error; MLX5_ASSERT (!rule_acts[act_data->action_dst + 1].action); rule_acts[act_data->action_dst + 1].action = @@ -3272,7 +3301,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, flow->jump = jump; flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP; if (mlx5_aso_mtr_wait(priv->sh, MLX5_HW_INV_QUEUE, aso_mtr)) - return -1; + goto error; break; case RTE_FLOW_ACTION_TYPE_AGE: aux = mlx5_flow_hw_aux(dev->data->port_id, flow); @@ -3288,7 +3317,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, flow->res_idx, error); if (age_idx == 0) - return -rte_errno; + goto error; mlx5_flow_hw_aux_set_age_idx(flow, aux, age_idx); flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX; if (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT) @@ -3303,7 +3332,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, cnt_queue = mlx5_hws_cnt_get_queue(priv, &queue); ret = mlx5_hws_cnt_pool_get(priv->hws_cpool, cnt_queue, &cnt_id, age_idx); if (ret != 0) - return ret; + goto error; ret = mlx5_hws_cnt_pool_get_action_offset (priv->hws_cpool, cnt_id, @@ -3311,7 +3340,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, &rule_acts[act_data->action_dst].counter.offset ); if (ret != 0) - return ret; + goto error; flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID; flow->cnt_id = cnt_id; break; @@ -3323,7 +3352,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, &rule_acts[act_data->action_dst].counter.offset ); if (ret != 0) - return ret; + goto error; flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID; flow->cnt_id = act_data->shared_counter.id; break; @@ -3331,7 +3360,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, ct_idx = MLX5_INDIRECT_ACTION_IDX_GET(action->conf); if (flow_hw_ct_compile(dev, queue, ct_idx, &rule_acts[act_data->action_dst])) - return -1; + goto error; break; case MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK: mtr_id = act_data->shared_meter.id & @@ -3339,7 +3368,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, /* Find ASO object. */ aso_mtr = mlx5_ipool_get(pool->idx_pool, mtr_id); if (!aso_mtr) - return -1; + goto error; rule_acts[act_data->action_dst].action = pool->action; rule_acts[act_data->action_dst].aso_meter.offset = @@ -3354,7 +3383,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, act_data->action_dst, action, rule_acts, &mtr_idx, MLX5_HW_INV_QUEUE, error); if (ret != 0) - return ret; + goto error; aux = mlx5_flow_hw_aux(dev->data->port_id, flow); mlx5_flow_hw_aux_set_mtr_id(flow, aux, mtr_idx); flow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MTR_ID; @@ -3396,11 +3425,11 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, struct mlx5dr_rule_action *ra = &rule_acts[hw_acts->encap_decap_pos]; if (ix < 0) - return -1; + goto error; if (!mp_segment) mp_segment = mlx5_multi_pattern_segment_find(table, flow->res_idx); if (!mp_segment || !mp_segment->reformat_action[ix]) - return -1; + goto error; ra->action = mp_segment->reformat_action[ix]; /* reformat offset is relative to selected DR action */ ra->reformat.offset = flow->res_idx - mp_segment->head_index; @@ -3416,6 +3445,11 @@ flow_hw_actions_construct(struct rte_eth_dev *dev, flow->cnt_id = hw_acts->cnt_id; } return 0; + +error: + flow_hw_release_actions(dev, queue, flow); + rte_errno = EINVAL; + return -rte_errno; } static const struct rte_flow_item * @@ -3565,10 +3599,8 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev, if (flow_hw_actions_construct(dev, flow, &ap, &table->ats[action_template_index], pattern_template_index, actions, - rule_acts, queue, error)) { - rte_errno = EINVAL; + rule_acts, queue, error)) goto error; - } rule_items = flow_hw_get_rule_items(dev, table, items, pattern_template_index, &pp); if (!rule_items)