From patchwork Mon Mar 25 09:14:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 51619 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 308A93798; Mon, 25 Mar 2019 10:15:14 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by dpdk.org (Postfix) with ESMTP id 3C9A4324D; Mon, 25 Mar 2019 10:15:11 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4F32C15BE; Mon, 25 Mar 2019 02:15:11 -0700 (PDT) Received: from net-arm-thunderx2.shanghai.arm.com (net-arm-thunderx2.shanghai.arm.com [10.169.40.112]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 723253F614; Mon, 25 Mar 2019 02:15:09 -0700 (PDT) From: Joyce Kong To: dev@dpdk.org Cc: nd@arm.com, jerinj@marvell.com, konstantin.ananyev@intel.com, chaozhu@linux.vnet.ibm.com, bruce.richardson@intel.com, thomas@monjalon.net, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, gavin.hu@arm.com, stable@dpdk.org Date: Mon, 25 Mar 2019 17:14:57 +0800 Message-Id: <1553505299-34459-2-git-send-email-joyce.kong@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553505299-34459-1-git-send-email-joyce.kong@arm.com> References: <1553505299-34459-1-git-send-email-joyce.kong@arm.com> In-Reply-To: <1544672265-219262-2-git-send-email-joyce.kong@arm.com> References: <1544672265-219262-2-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v5 1/3] rwlock: reimplement with atomic builtins X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The __sync builtin based implementation generates full memory barriers ('dmb ish') on Arm platforms. Using C11 atomic builtins to generate one way barriers. Here is the assembly code of __sync_compare_and_swap builtin. __sync_bool_compare_and_swap(dst, exp, src); 0x000000000090f1b0 <+16>: e0 07 40 f9 ldr x0, [sp, #8] 0x000000000090f1b4 <+20>: e1 0f 40 79 ldrh w1, [sp, #6] 0x000000000090f1b8 <+24>: e2 0b 40 79 ldrh w2, [sp, #4] 0x000000000090f1bc <+28>: 21 3c 00 12 and w1, w1, #0xffff 0x000000000090f1c0 <+32>: 03 7c 5f 48 ldxrh w3, [x0] 0x000000000090f1c4 <+36>: 7f 00 01 6b cmp w3, w1 0x000000000090f1c8 <+40>: 61 00 00 54 b.ne 0x90f1d4 // b.any 0x000000000090f1cc <+44>: 02 fc 04 48 stlxrh w4, w2, [x0] 0x000000000090f1d0 <+48>: 84 ff ff 35 cbnz w4, 0x90f1c0 0x000000000090f1d4 <+52>: bf 3b 03 d5 dmb ish 0x000000000090f1d8 <+56>: e0 17 9f 1a cset w0, eq // eq = none Fixes: af75078fece3 ("first public release") Cc: stable@dpdk.org Signed-off-by: Gavin Hu Signed-off-by: Joyce Kong Tested-by: Joyce Kong Acked-by: Jerin Jacob Acked-by: Konstantin Ananyev --- lib/librte_eal/common/include/generic/rte_rwlock.h | 29 +++++++++++----------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/lib/librte_eal/common/include/generic/rte_rwlock.h b/lib/librte_eal/common/include/generic/rte_rwlock.h index b05d85a..31608fa 100644 --- a/lib/librte_eal/common/include/generic/rte_rwlock.h +++ b/lib/librte_eal/common/include/generic/rte_rwlock.h @@ -64,14 +64,14 @@ rte_rwlock_read_lock(rte_rwlock_t *rwl) int success = 0; while (success == 0) { - x = rwl->cnt; + x = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED); /* write lock is held */ if (x < 0) { rte_pause(); continue; } - success = rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt, - (uint32_t)x, (uint32_t)(x + 1)); + success = __atomic_compare_exchange_n(&rwl->cnt, &x, x + 1, 1, + __ATOMIC_ACQUIRE, __ATOMIC_RELAXED); } } @@ -95,13 +95,14 @@ rte_rwlock_read_trylock(rte_rwlock_t *rwl) int success = 0; while (success == 0) { - x = rwl->cnt; + x = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED); /* write lock is held */ if (x < 0) return -EBUSY; - success = rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt, - (uint32_t)x, (uint32_t)(x + 1)); + success = __atomic_compare_exchange_n(&rwl->cnt, &x, x + 1, 1, + __ATOMIC_ACQUIRE, __ATOMIC_RELAXED); } + return 0; } @@ -114,7 +115,7 @@ rte_rwlock_read_trylock(rte_rwlock_t *rwl) static inline void rte_rwlock_read_unlock(rte_rwlock_t *rwl) { - rte_atomic32_dec((rte_atomic32_t *)(intptr_t)&rwl->cnt); + __atomic_fetch_sub(&rwl->cnt, 1, __ATOMIC_RELEASE); } /** @@ -135,9 +136,9 @@ rte_rwlock_write_trylock(rte_rwlock_t *rwl) { int32_t x; - x = rwl->cnt; - if (x != 0 || rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt, - 0, (uint32_t)-1) == 0) + x = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED); + if (x != 0 || __atomic_compare_exchange_n(&rwl->cnt, &x, -1, 1, + __ATOMIC_ACQUIRE, __ATOMIC_RELAXED) == 0) return -EBUSY; return 0; @@ -156,14 +157,14 @@ rte_rwlock_write_lock(rte_rwlock_t *rwl) int success = 0; while (success == 0) { - x = rwl->cnt; + x = __atomic_load_n(&rwl->cnt, __ATOMIC_RELAXED); /* a lock is held */ if (x != 0) { rte_pause(); continue; } - success = rte_atomic32_cmpset((volatile uint32_t *)&rwl->cnt, - 0, (uint32_t)-1); + success = __atomic_compare_exchange_n(&rwl->cnt, &x, -1, 1, + __ATOMIC_ACQUIRE, __ATOMIC_RELAXED); } } @@ -176,7 +177,7 @@ rte_rwlock_write_lock(rte_rwlock_t *rwl) static inline void rte_rwlock_write_unlock(rte_rwlock_t *rwl) { - rte_atomic32_inc((rte_atomic32_t *)(intptr_t)&rwl->cnt); + __atomic_store_n(&rwl->cnt, 0, __ATOMIC_RELEASE); } /** From patchwork Mon Mar 25 09:14:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 51620 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C91204C94; Mon, 25 Mar 2019 10:15:17 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by dpdk.org (Postfix) with ESMTP id A94B544C3; Mon, 25 Mar 2019 10:15:14 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6EB7E168F; Mon, 25 Mar 2019 02:15:13 -0700 (PDT) Received: from net-arm-thunderx2.shanghai.arm.com (net-arm-thunderx2.shanghai.arm.com [10.169.40.112]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8B11F3F614; Mon, 25 Mar 2019 02:15:11 -0700 (PDT) From: Joyce Kong To: dev@dpdk.org Cc: nd@arm.com, jerinj@marvell.com, konstantin.ananyev@intel.com, chaozhu@linux.vnet.ibm.com, bruce.richardson@intel.com, thomas@monjalon.net, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, gavin.hu@arm.com, stable@dpdk.org Date: Mon, 25 Mar 2019 17:14:58 +0800 Message-Id: <1553505299-34459-3-git-send-email-joyce.kong@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553505299-34459-1-git-send-email-joyce.kong@arm.com> References: <1553505299-34459-1-git-send-email-joyce.kong@arm.com> In-Reply-To: <1544672265-219262-2-git-send-email-joyce.kong@arm.com> References: <1544672265-219262-2-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v5 2/3] test/rwlock: add perf test case on all available cores X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add performance test on all available cores to benchmark the scaling up performance of rw_lock. Fixes: af75078fece3 ("first public release") Cc: stable@dpdk.org Suggested-by: Gavin Hu Signed-off-by: Joyce Kong Acked-by: Konstantin Ananyev --- app/test/test_rwlock.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/app/test/test_rwlock.c b/app/test/test_rwlock.c index 224f0de..1d3774e 100644 --- a/app/test/test_rwlock.c +++ b/app/test/test_rwlock.c @@ -36,6 +36,7 @@ static rte_rwlock_t sl; static rte_rwlock_t sl_tab[RTE_MAX_LCORE]; +static rte_atomic32_t synchro; enum { LC_TYPE_RDLOCK, @@ -83,6 +84,77 @@ test_rwlock_per_core(__attribute__((unused)) void *arg) return 0; } +static rte_rwlock_t lk = RTE_RWLOCK_INITIALIZER; +static volatile uint64_t rwlock_data; +static uint64_t lock_count[RTE_MAX_LCORE] = {0}; + +#define TIME_MS 100 +#define TEST_RWLOCK_DEBUG 0 + +static int +load_loop_fn(__attribute__((unused)) void *arg) +{ + uint64_t time_diff = 0, begin; + uint64_t hz = rte_get_timer_hz(); + uint64_t lcount = 0; + const unsigned int lcore = rte_lcore_id(); + + /* wait synchro for slaves */ + if (lcore != rte_get_master_lcore()) + while (rte_atomic32_read(&synchro) == 0) + ; + + begin = rte_rdtsc_precise(); + while (time_diff < hz * TIME_MS / 1000) { + rte_rwlock_write_lock(&lk); + ++rwlock_data; + rte_rwlock_write_unlock(&lk); + + rte_rwlock_read_lock(&lk); + if (TEST_RWLOCK_DEBUG && !(lcount % 100)) + printf("Core [%u] rwlock_data = %"PRIu64"\n", + lcore, rwlock_data); + rte_rwlock_read_unlock(&lk); + + lcount++; + /* delay to make lock duty cycle slightly realistic */ + rte_pause(); + time_diff = rte_rdtsc_precise() - begin; + } + + lock_count[lcore] = lcount; + return 0; +} + +static int +test_rwlock_perf(void) +{ + unsigned int i; + uint64_t total = 0; + + printf("\nRwlock Perf Test on %u cores...\n", rte_lcore_count()); + + /* clear synchro and start slaves */ + rte_atomic32_set(&synchro, 0); + if (rte_eal_mp_remote_launch(load_loop_fn, NULL, SKIP_MASTER) < 0) + return -1; + + /* start synchro and launch test on master */ + rte_atomic32_set(&synchro, 1); + load_loop_fn(NULL); + + rte_eal_mp_wait_lcore(); + + RTE_LCORE_FOREACH(i) { + printf("Core [%u] count = %"PRIu64"\n", i, lock_count[i]); + total += lock_count[i]; + } + + printf("Total count = %"PRIu64"\n", total); + + return 0; +} + /* * - There is a global rwlock and a table of rwlocks (one per lcore). * @@ -132,6 +204,9 @@ rwlock_test1(void) rte_eal_mp_wait_lcore(); + if (test_rwlock_perf() < 0) + return -1; + return 0; } From patchwork Mon Mar 25 09:14:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joyce Kong X-Patchwork-Id: 51621 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id EDACA4CA7; Mon, 25 Mar 2019 10:15:20 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.101.70]) by dpdk.org (Postfix) with ESMTP id 23172493D; Mon, 25 Mar 2019 10:15:16 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 90AE015AB; Mon, 25 Mar 2019 02:15:15 -0700 (PDT) Received: from net-arm-thunderx2.shanghai.arm.com (net-arm-thunderx2.shanghai.arm.com [10.169.40.112]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id AC9F53F614; Mon, 25 Mar 2019 02:15:13 -0700 (PDT) From: Joyce Kong To: dev@dpdk.org Cc: nd@arm.com, jerinj@marvell.com, konstantin.ananyev@intel.com, chaozhu@linux.vnet.ibm.com, bruce.richardson@intel.com, thomas@monjalon.net, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, gavin.hu@arm.com, stable@dpdk.org Date: Mon, 25 Mar 2019 17:14:59 +0800 Message-Id: <1553505299-34459-4-git-send-email-joyce.kong@arm.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1553505299-34459-1-git-send-email-joyce.kong@arm.com> References: <1553505299-34459-1-git-send-email-joyce.kong@arm.com> In-Reply-To: <1544672265-219262-2-git-send-email-joyce.kong@arm.com> References: <1544672265-219262-2-git-send-email-joyce.kong@arm.com> Subject: [dpdk-dev] [PATCH v5 3/3] test/rwlock: amortize the cost of getting time X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Instead of getting timestamp per iteration, amortize its overhead can help to get more precise benchmarking results. Fixes: af75078fece3 ("first public release") Cc: stable@dpdk.org Signed-off-by: Joyce Kong Acked-by: Konstantin Ananyev --- app/test/test_rwlock.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/app/test/test_rwlock.c b/app/test/test_rwlock.c index 1d3774e..c3d656a 100644 --- a/app/test/test_rwlock.c +++ b/app/test/test_rwlock.c @@ -86,9 +86,9 @@ test_rwlock_per_core(__attribute__((unused)) void *arg) static rte_rwlock_t lk = RTE_RWLOCK_INITIALIZER; static volatile uint64_t rwlock_data; -static uint64_t lock_count[RTE_MAX_LCORE] = {0}; +static uint64_t time_count[RTE_MAX_LCORE] = {0}; -#define TIME_MS 100 +#define MAX_LOOP 10000 #define TEST_RWLOCK_DEBUG 0 static int @@ -105,7 +105,7 @@ load_loop_fn(__attribute__((unused)) void *arg) ; begin = rte_rdtsc_precise(); - while (time_diff < hz * TIME_MS / 1000) { + while (lcount < MAX_LOOP) { rte_rwlock_write_lock(&lk); ++rwlock_data; rte_rwlock_write_unlock(&lk); @@ -119,10 +119,10 @@ load_loop_fn(__attribute__((unused)) void *arg) lcount++; /* delay to make lock duty cycle slightly realistic */ rte_pause(); - time_diff = rte_rdtsc_precise() - begin; } - lock_count[lcore] = lcount; + time_diff = rte_rdtsc_precise() - begin; + time_count[lcore] = time_diff * 1000000 / hz; return 0; } @@ -146,11 +146,13 @@ test_rwlock_perf(void) rte_eal_mp_wait_lcore(); RTE_LCORE_FOREACH(i) { - printf("Core [%u] count = %"PRIu64"\n", i, lock_count[i]); - total += lock_count[i]; + printf("Core [%u] cost time = %"PRIu64" us\n", + i, time_count[i]); + total += time_count[i]; } - printf("Total count = %"PRIu64"\n", total); + printf("Total cost time = %"PRIu64" us\n", total); + memset(time_count, 0, sizeof(time_count)); return 0; }