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{ "id": 95658, "url": "http://patchwork.dpdk.org/api/covers/95658/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/cover/20210712014654.32428-1-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210712014654.32428-1-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210712014654.32428-1-suanmingm@nvidia.com", "date": "2021-07-12T01:46:28", "name": "[v5,00/26] net/mlx5: insertion rate optimization", "submitter": { "id": 1887, "url": "http://patchwork.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/cover/20210712014654.32428-1-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17759, "url": "http://patchwork.dpdk.org/api/series/17759/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17759", "date": "2021-07-12T01:46:29", "name": "net/mlx5: insertion rate optimization", "version": 5, "mbox": "http://patchwork.dpdk.org/series/17759/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/covers/95658/comments/", "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C8905A0C4B;\n\tMon, 12 Jul 2021 03:47:35 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3C91741169;\n\tMon, 12 Jul 2021 03:47:30 +0200 (CEST)", "from NAM02-DM3-obe.outbound.protection.outlook.com\n (mail-dm3nam07on2065.outbound.protection.outlook.com [40.107.95.65])\n by mails.dpdk.org (Postfix) with ESMTP id 0684640685\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Date": "Mon, 12 Jul 2021 04:46:28 +0300", "Message-ID": "<20210712014654.32428-1-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20210527093403.1153127-1-suanmingm@nvidia.com>", "References": "<20210527093403.1153127-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.5]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "e5629bff-71a1-4a45-7202-08d944d6fffb", "X-MS-TrafficTypeDiagnostic": "BN6PR12MB1250:", "X-Microsoft-Antispam-PRVS": "\n <BN6PR12MB12501DCD7DCB9521B6271222C1159@BN6PR12MB1250.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:8273;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n +wPNzcmaIlVwzA7B/FpXxSMWIKRionQcNaG+OroYtBWnRF+B9wDod68ZGPzXCtvsZq9phi6IDafDIoDZ26LpGGpP672o+Nb5NsahQyFQFbt7sf1sgb7oNjaZRtSzEThKQlzjKwNNzdldvDZkO7DVKsaw7kRka9oRKbmA7TOLUVViscSH+l/pfDNTRcjiOgHjRsBhrRekgfc4CbZG3zf96AelgL1Xk00ppvNFER0msYkuqvXrB6oLJ12tKXXAdmzos/kaDPbt39JYdjBAnXUVjnTA7kMZ6smQ6FBgNZf7gU2OhLVVriAGVwiquP+es0L12YArf5WMiteeFpbmIzGA/ABnCQQurWe4ZC7W23FA/eeI0z1CqDVSgjEjC2QVopg1Q1BxwTHID8udIQcE+2Cr6BLa2KMHrpcDNfGat6dUxfwo8sujBmsz5bpRnKoeBvzZlB+0GgTKvzJivr4WUPD3EGeP3kbFRvD0r1rPVAMAfxj8x5FWvHJGf1ENvwkgzOPXY977XiRU5yuB2jgA8U32vdYsrYgqtp1KKX5Fsjw2EQD4DDJrfboeI+PMmqoJn26PSG/g3HWwU3OZCpmZatmUcpKsZzU8ItOVDFDSirjelqIgAK+VzfeJrBT3ON9Jp4XPTypcW+bTGoVC2795XDDdFRYgQo345SFw6R0neIQSy2/PnpOffvbuBQG+W+LGOOEZW4Lu64H38trTxdT13ta9D/dLp60zgXMyAn1RO+ei0g0=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(136003)(376002)(39860400002)(346002)(396003)(46966006)(36840700001)(1076003)(8676002)(16526019)(356005)(86362001)(70586007)(2906002)(82310400003)(5660300002)(6636002)(6666004)(70206006)(8936002)(36756003)(336012)(26005)(36860700001)(7636003)(6286002)(47076005)(83380400001)(186003)(110136005)(4326008)(7696005)(478600001)(55016002)(426003)(2616005)(36906005)(54906003)(82740400003)(34020700004)(316002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "12 Jul 2021 01:47:25.5865 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e5629bff-71a1-4a45-7202-08d944d6fffb", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT009.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN6PR12MB1250", "Subject": "[dpdk-dev] [PATCH v5 00/26] net/mlx5: insertion rate optimization", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch series optimize the flow insertion rate with adding\nlocal cache to index pool and list.\n\nFor object which wants efficient index allocate and free, local\ncache will be very helpful.\n\nFor index pool, two level cache is added, one as local and another\nas global. The global cache is able to save all the allocated\nindex. That means all the allocated index will not be freed. Once\nthe local cache is full, the extra index will be flushed to the\nglobal cache. Once local cache is empty, first try to fetch more\nindex from global, if global is still empty, allocate new trunk\nand more index.\n\nFor list, sub local core list is introduced. The allocated objects\nwill be added and released only from local list without any locks.\nOnly the objects need to be shared will be synced from global list.\n\n---\n\nv5: code rebase to the latest version.\n\nv4:\n - split the list utility to commom patch\n - fix one ipool crash issue in mlx5_ipool_get_cache() function.\n - reorganize the common and mlx5 patches.\n - split the doc update to an individual patch.\n - update and rebase to the latest version.\n\nv3: fix Windows compilation issue\n\nv2: add the list per-lcore cache optimization\n\n---\n\nMatan Azrad (9):\n net/mlx5: optimize modify header action memory\n net/mlx5: remove cache term from the list utility\n net/mlx5: add per lcore cache to the list utility\n net/mlx5: minimize list critical sections\n net/mlx5: manage list cache entries release\n net/mlx5: relax the list utility atomic operations\n net/mlx5: allocate list memory by the create API\n common/mlx5: add per-lcore cache to hash list utility\n net/mlx5: move modify header allocator to ipool\n\nSuanming Mou (17):\n net/mlx5: allow limiting the index pool maximum index\n net/mlx5: add indexed pool local cache\n net/mlx5: add index pool foreach define\n net/mlx5: support index pool non-lcore operations\n net/mlx5: replace flow list with index pool\n common/mlx5: move list utility to common\n common/mlx5: add list lcore share\n common/mlx5: call list callbacks with context\n common/mlx5: allocate cache list memory individually\n common/mlx5: optimize cache list object memory\n common/mlx5: support list non-lcore operations\n net/mlx5: adjust the hash bucket size\n net/mlx5: enable index pool per-core cache\n net/mlx5: optimize hash list table allocate on demand\n net/mlx5: change memory release configuration\n net/mlx5: optimize Rx queue match\n doc: add mlx5 multiple-thread flow insertion optimization\n\n doc/guides/nics/mlx5.rst | 5 +\n doc/guides/rel_notes/release_21_08.rst | 1 +\n drivers/common/mlx5/linux/mlx5_glue.h | 1 +\n drivers/common/mlx5/mlx5_common.h | 2 +\n drivers/common/mlx5/mlx5_common_utils.c | 569 ++++++++---\n drivers/common/mlx5/mlx5_common_utils.h | 294 ++++--\n drivers/common/mlx5/version.map | 7 +\n drivers/net/mlx5/linux/mlx5_flow_os.h | 3 +-\n drivers/net/mlx5/linux/mlx5_os.c | 209 ++--\n drivers/net/mlx5/mlx5.c | 34 +-\n drivers/net/mlx5/mlx5.h | 46 +-\n drivers/net/mlx5/mlx5_defs.h | 12 +-\n drivers/net/mlx5/mlx5_flow.c | 308 +++---\n drivers/net/mlx5/mlx5_flow.h | 209 ++--\n drivers/net/mlx5/mlx5_flow_dv.c | 1206 +++++++++++++++--------\n drivers/net/mlx5/mlx5_rx.h | 14 +-\n drivers/net/mlx5/mlx5_rxq.c | 136 ++-\n drivers/net/mlx5/mlx5_trigger.c | 8 +-\n drivers/net/mlx5/mlx5_utils.c | 627 ++++++++----\n drivers/net/mlx5/mlx5_utils.h | 255 ++---\n drivers/net/mlx5/windows/mlx5_os.c | 11 +-\n 21 files changed, 2543 insertions(+), 1414 deletions(-)" }