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GET /api/patches/117921/?format=api
{ "id": 117921, "url": "http://patchwork.dpdk.org/api/patches/117921/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20221011120135.45846-2-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221011120135.45846-2-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221011120135.45846-2-ndabilpuram@marvell.com", "date": "2022-10-11T12:01:24", "name": "[02/13] common/cnxk: add devargs for soft expiry poll frequency", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "f246e804edb7079e48c6125a8569faa5a7d3b709", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20221011120135.45846-2-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 25145, "url": "http://patchwork.dpdk.org/api/series/25145/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=25145", "date": "2022-10-11T12:01:23", "name": "[01/13] common/cnxk: set MTU size on SDP based on SoC type", "version": 1, "mbox": "http://patchwork.dpdk.org/series/25145/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/117921/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/117921/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9E6AEA0545;\n\tTue, 11 Oct 2022 14:03:55 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7248842CCB;\n\tTue, 11 Oct 2022 14:03:55 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id C5F0E42B7D\n for <dev@dpdk.org>; Tue, 11 Oct 2022 14:03:53 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 29B1Na3t011947;\n Tue, 11 Oct 2022 05:01:45 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3k40g4y26k-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 11 Oct 2022 05:01:45 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 11 Oct 2022 05:01:43 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 11 Oct 2022 05:01:43 -0700", "from localhost.localdomain (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 5B2343F705A;\n Tue, 11 Oct 2022 05:01:41 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=YwJP4LnOkqqCFpsdjvFtEoi9bFXiveK7Y7MoreG2D9o=;\n b=JMsVnqYoHC/QHem3iBHGZyKgkPzm0Mqtzo68DWSwL4zmzPz86k92DUe9kvh0AMaWgOL/\n xxvZitf3fZ+jUg5jQ+gsVnv4+3izKKnc/p0Q2I4mswwr5TWMSuy0Eu/WpB3EFaf9BWay\n pa2CWkSHeeShPSAff3jLvw3Pu4qA51Vt/0stuNMI6v+uV3GyUXL2VK6ofcgMBJdcb2c2\n eB47Cs51SuswyzY/1WWIpuVr1zWKQuX6Yv2qsYA3MGQcwT8cPLNc8bQ3CHcfpo1SnyPw\n TMCrW2uAyGCXW6z5lqSCXIOjrMc6cO6C0WDPCEF6592w38mYK1ev7VuC8do/xs+yrBcm 5g==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 02/13] common/cnxk: add devargs for soft expiry poll frequency", "Date": "Tue, 11 Oct 2022 17:31:24 +0530", "Message-ID": "<20221011120135.45846-2-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20221011120135.45846-1-ndabilpuram@marvell.com>", "References": "<20221011120135.45846-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "RLcJsHeRVAXpqEmgOG9BdVQp7TWhM3xb", "X-Proofpoint-GUID": "RLcJsHeRVAXpqEmgOG9BdVQp7TWhM3xb", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1\n definitions=2022-10-11_07,2022-10-11_02,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support to override soft expiry poll frequency via devargs.\nAlso provide helper API to indicate reassembly support on a chip\nand documentation for devargs that are already present.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n doc/guides/nics/cnxk.rst | 39 +++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_inl.c | 7 +++++\n drivers/common/cnxk/roc_nix_inl.h | 3 ++-\n drivers/common/cnxk/roc_nix_inl_dev.c | 4 +--\n drivers/common/cnxk/version.map | 1 +\n drivers/net/cnxk/cnxk_ethdev_sec.c | 17 +++++++++---\n 6 files changed, 65 insertions(+), 6 deletions(-)", "diff": "diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex a1e3a4a965..7da6cb3967 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -494,6 +494,45 @@ Runtime Config Options for inline device\n With the above configuration, application can enable inline IPsec processing\n for inbound SA with max SPI of 128 for traffic aggregated on inline device.\n \n+- ``Count of meta buffers for inline inbound IPsec second pass``\n+\n+ Number of meta buffers allocated for inline inbound IPsec second pass can\n+ be specified by ``nb_meta_bufs`` ``devargs`` parameter. Default value is\n+ computed runtime based on pkt mbuf pools created and in use. Number of meta\n+ buffers should be at least equal to aggregated number of packet buffers of all\n+ packet mbuf pools in use by Inline IPsec enabled ethernet devices.\n+\n+ For example::\n+\n+ -a 0002:1d:00.0,nb_meta_bufs=1024\n+\n+ With the above configuration, PMD would enable inline IPsec processing\n+ for inbound with 1024 meta buffers available for second pass.\n+\n+- ``Meta buffer size for inline inbound IPsec second pass``\n+\n+ Size of meta buffer allocated for inline inbound IPsec second pass can\n+ be specified by ``meta_buf_sz`` ``devargs`` parameter. Default value is\n+ computed runtime based on pkt mbuf pools created and in use.\n+\n+ For example::\n+\n+ -a 0002:1d:00.0,meta_buf_sz=512\n+\n+ With the above configuration, PMD would allocate meta buffers of size 512 for\n+ inline inbound IPsec processing second pass.\n+\n+- ``Inline Outbound soft expiry poll frequency in usec`` (default ``100``)\n+\n+ Soft expiry poll frequency for Inline Outbound sessions can be specified by\n+ ``soft_exp_poll_freq`` ``devargs`` parameter.\n+\n+ For example::\n+\n+ -a 0002:1d:00.0,soft_exp_poll_freq=1000\n+\n+ With the above configuration, driver would poll for soft expiry events every\n+ 1000 usec.\n \n Debugging Options\n -----------------\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex cdf31b1f0c..213d71e684 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -480,6 +480,13 @@ nix_inl_rq_mask_cfg(struct roc_nix *roc_nix, bool enable)\n \treturn mbox_process(mbox);\n }\n \n+bool\n+roc_nix_has_reass_support(struct roc_nix *nix)\n+{\n+\tPLT_SET_USED(nix);\n+\treturn !!roc_model_is_cn10ka();\n+}\n+\n int\n roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n {\ndiff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h\nindex 019cf6d28b..c537262819 100644\n--- a/drivers/common/cnxk/roc_nix_inl.h\n+++ b/drivers/common/cnxk/roc_nix_inl.h\n@@ -183,7 +183,7 @@ struct roc_nix_inl_dev {\n \tuint16_t wqe_skip;\n \tuint8_t spb_drop_pc;\n \tuint8_t lpb_drop_pc;\n-\tbool set_soft_exp_poll;\n+\tuint32_t soft_exp_poll_freq; /* Polling disabled if 0 */\n \tuint32_t nb_meta_bufs;\n \tuint32_t meta_buf_sz;\n \t/* End of input parameters */\n@@ -229,6 +229,7 @@ int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena,\n \t\t\t\t bool inb_inl_dev);\n int __roc_api roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool ena);\n int __roc_api roc_nix_inl_meta_aura_check(struct roc_nix_rq *rq);\n+bool __roc_api roc_nix_has_reass_support(struct roc_nix *nix);\n \n /* NIX Inline Outbound API */\n int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix);\ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c\nindex 4fe7b5180b..c3d94dd0da 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev.c\n@@ -789,7 +789,6 @@ nix_inl_outb_poll_thread_setup(struct nix_inl_dev *inl_dev)\n \n \tsoft_exp_consumer_cnt = 0;\n \tsoft_exp_poll_thread_exit = false;\n-\tinl_dev->soft_exp_poll_freq = 100;\n \trc = plt_ctrl_thread_create(&inl_dev->soft_exp_poll_thread,\n \t\t\t\t \"OUTB_SOFT_EXP_POLL_THREAD\", NULL,\n \t\t\t\t nix_inl_outb_poll_thread, inl_dev);\n@@ -839,10 +838,11 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)\n \tinl_dev->wqe_skip = roc_inl_dev->wqe_skip;\n \tinl_dev->spb_drop_pc = NIX_AURA_DROP_PC_DFLT;\n \tinl_dev->lpb_drop_pc = NIX_AURA_DROP_PC_DFLT;\n-\tinl_dev->set_soft_exp_poll = roc_inl_dev->set_soft_exp_poll;\n+\tinl_dev->set_soft_exp_poll = !!roc_inl_dev->soft_exp_poll_freq;\n \tinl_dev->nb_rqs = inl_dev->is_multi_channel ? 1 : PLT_MAX_ETHPORTS;\n \tinl_dev->nb_meta_bufs = roc_inl_dev->nb_meta_bufs;\n \tinl_dev->meta_buf_sz = roc_inl_dev->meta_buf_sz;\n+\tinl_dev->soft_exp_poll_freq = roc_inl_dev->soft_exp_poll_freq;\n \n \tif (roc_inl_dev->spb_drop_pc)\n \t\tinl_dev->spb_drop_pc = roc_inl_dev->spb_drop_pc;\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 276fec3660..f08b6076e4 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -135,6 +135,7 @@ INTERNAL {\n \troc_nix_get_pf_func;\n \troc_nix_get_vf;\n \troc_nix_get_vwqe_interval;\n+\troc_nix_has_reass_support;\n \troc_nix_inl_cb_register;\n \troc_nix_inl_cb_unregister;\n \troc_nix_inl_ctx_write;\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_sec.c b/drivers/net/cnxk/cnxk_ethdev_sec.c\nindex 9304b1465d..8bec9acb54 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_sec.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_sec.c\n@@ -12,6 +12,10 @@\n #define CNXK_INL_CPT_CHANNEL\t \"inl_cpt_channel\"\n #define CNXK_NIX_INL_NB_META_BUFS \"nb_meta_bufs\"\n #define CNXK_NIX_INL_META_BUF_SZ \"meta_buf_sz\"\n+#define CNXK_NIX_SOFT_EXP_POLL_FREQ \"soft_exp_poll_freq\"\n+\n+/* Default soft expiry poll freq in usec */\n+#define CNXK_NIX_SOFT_EXP_POLL_FREQ_DFLT 100\n \n struct inl_cpt_channel {\n \tbool is_multi_channel;\n@@ -263,6 +267,7 @@ static int\n nix_inl_parse_devargs(struct rte_devargs *devargs,\n \t\t struct roc_nix_inl_dev *inl_dev)\n {\n+\tuint32_t soft_exp_poll_freq = CNXK_NIX_SOFT_EXP_POLL_FREQ_DFLT;\n \tuint32_t ipsec_in_max_spi = BIT(8) - 1;\n \tuint32_t ipsec_in_min_spi = 0;\n \tstruct inl_cpt_channel cpt_channel;\n@@ -292,6 +297,8 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,\n \t\t\t &nb_meta_bufs);\n \trte_kvargs_process(kvlist, CNXK_NIX_INL_META_BUF_SZ, &parse_val_u32,\n \t\t\t &meta_buf_sz);\n+\trte_kvargs_process(kvlist, CNXK_NIX_SOFT_EXP_POLL_FREQ,\n+\t\t\t &parse_val_u32, &soft_exp_poll_freq);\n \trte_kvargs_free(kvlist);\n \n null_devargs:\n@@ -303,6 +310,7 @@ nix_inl_parse_devargs(struct rte_devargs *devargs,\n \tinl_dev->is_multi_channel = cpt_channel.is_multi_channel;\n \tinl_dev->nb_meta_bufs = nb_meta_bufs;\n \tinl_dev->meta_buf_sz = meta_buf_sz;\n+\tinl_dev->soft_exp_poll_freq = soft_exp_poll_freq;\n \treturn 0;\n exit:\n \treturn -EINVAL;\n@@ -390,7 +398,6 @@ cnxk_nix_inl_dev_probe(struct rte_pci_driver *pci_drv,\n \twqe_skip = RTE_ALIGN_CEIL(sizeof(struct rte_mbuf), ROC_CACHE_LINE_SZ);\n \twqe_skip = wqe_skip / ROC_CACHE_LINE_SZ;\n \tinl_dev->wqe_skip = wqe_skip;\n-\tinl_dev->set_soft_exp_poll = true;\n \trc = roc_nix_inl_dev_init(inl_dev);\n \tif (rc) {\n \t\tplt_err(\"Failed to init nix inl device, rc=%d(%s)\", rc,\n@@ -425,5 +432,9 @@ RTE_PMD_REGISTER_KMOD_DEP(cnxk_nix_inl, \"vfio-pci\");\n \n RTE_PMD_REGISTER_PARAM_STRING(cnxk_nix_inl,\n \t\t\t CNXK_NIX_INL_SELFTEST \"=1\"\n-\t\t\t CNXK_NIX_INL_IPSEC_IN_MAX_SPI \"=<1-65535>\"\n-\t\t\t CNXK_INL_CPT_CHANNEL \"=<1-4095>/<1-4095>\");\n+\t\t\t CNXK_NIX_INL_IPSEC_IN_MIN_SPI \"=<1-U32_MAX>\"\n+\t\t\t CNXK_NIX_INL_IPSEC_IN_MAX_SPI \"=<1-U32_MAX>\"\n+\t\t\t CNXK_INL_CPT_CHANNEL \"=<1-4095>/<1-4095>\"\n+\t\t\t CNXK_NIX_INL_NB_META_BUFS \"=<1-U32_MAX>\"\n+\t\t\t CNXK_NIX_INL_META_BUF_SZ \"=<1-U32_MAX>\"\n+\t\t\t CNXK_NIX_SOFT_EXP_POLL_FREQ \"=<0-U32_MAX>\");\n", "prefixes": [ "02/13" ] }