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GET /api/patches/122789/?format=api
{ "id": 122789, "url": "http://patchwork.dpdk.org/api/patches/122789/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230201072815.1329101-12-valex@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230201072815.1329101-12-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230201072815.1329101-12-valex@nvidia.com", "date": "2023-02-01T07:28:10", "name": "[v2,11/16] net/mlx5/hws: support partial hash", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "bc74e0e61985edc97cbe5838ac294f98b6e0674e", "submitter": { "id": 2858, "url": "http://patchwork.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230201072815.1329101-12-valex@nvidia.com/mbox/", "series": [ { "id": 26726, "url": "http://patchwork.dpdk.org/api/series/26726/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=26726", "date": "2023-02-01T07:28:01", "name": "net/mlx5/hws: support range and partial hash matching", "version": 2, "mbox": "http://patchwork.dpdk.org/series/26726/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/122789/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/122789/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 32D5341B9B;\n\tWed, 1 Feb 2023 08:30:20 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C480542D5F;\n\tWed, 1 Feb 2023 08:29:22 +0100 (CET)", "from NAM02-DM3-obe.outbound.protection.outlook.com\n (mail-dm3nam02on2046.outbound.protection.outlook.com [40.107.95.46])\n by mails.dpdk.org (Postfix) with ESMTP id A9E5541151\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n \"Matan Azrad\" <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v2 11/16] net/mlx5/hws: support partial hash", "Date": "Wed, 1 Feb 2023 09:28:10 +0200", "Message-ID": "<20230201072815.1329101-12-valex@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20230201072815.1329101-1-valex@nvidia.com>", "References": "<20230131093346.1261066-1-valex@nvidia.com>\n <20230201072815.1329101-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT082:EE_|SA0PR12MB4445:EE_", "X-MS-Office365-Filtering-Correlation-Id": "304223a5-afe1-464f-cb87-08db0426071f", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 5WfDvLE0GX78tB2jtfVprPWRynG3CVrGrY8JoK3A0i8VD2bhQclL0FyLiu8q6SX2A4Vt7KBHtnSOCsjlKjndJ486w0zGPMtWhsIjqCDUonbqWds+15oMnzS++1ny6BCsPILsKEb00wxA2HP7jiNONPI5mz0YEbwkW7QCviNBJrtr8xGcL9evm/dMZieXL4Oj2p9BIS1TBfpadz+sLt8BRDGF7X2xadv24sP6a2qpdkbxKrHtKa0LOQzqqrtZB4syVNq1gyZGwe1Vj8CpE7dgw65uhx2MNdv2gg6VujGMZTB/q+MpUlyktQ7qGtg7kKDx9X+gvxVcShkq5nis0N4BZYMhtlU9j3EhDdBrJ7q/TMb2CcYgYSyM7rcwxca99708BORdt7NhtbOJmcwt7PhGq4mtaY1KGp7iC0HSe3ggw+PJ6JaFz/ZCw/odLeOanVsJjhGqFrCRWf9YSllHgFv9t7nxA3Zz6s5MEGVOHC6GbXDuE0+UewrJVTyZFSflwUUuz510OI/Ck4R8u/A0hf1IGcse52dU10h6AiGI85aG82FREpxiAgppFQ+SF3DYfI556etx8HJt2Z3Gr+tpvH1Ecm7w2VZ0Y+9OBCD/0mdHBmHMM3Hl15IlhFBQYea5MKfy6b2bUvtKf5QrZ6OqSnpe4/7+r/mj3qGF2aiSL+3zBcn+F/2GdRrBN4yYrNC8PQW2jDsEV9eewKb5Uj5yUfAulA==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230025)(4636009)(136003)(396003)(39860400002)(376002)(346002)(451199018)(46966006)(40470700004)(36840700001)(82740400003)(7636003)(6286002)(26005)(8676002)(356005)(54906003)(4326008)(6636002)(70586007)(110136005)(316002)(40460700003)(336012)(107886003)(1076003)(6666004)(186003)(2616005)(426003)(7696005)(16526019)(82310400005)(47076005)(70206006)(83380400001)(36756003)(55016003)(36860700001)(40480700001)(478600001)(2906002)(41300700001)(5660300002)(86362001)(30864003)(8936002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Feb 2023 07:29:17.5818 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 304223a5-afe1-464f-cb87-08db0426071f", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT082.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA0PR12MB4445", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Hash definers allow performing hashing over a subset of\nthe fields which are used for matching. This allows combining\nmatch templates which were considered invalid until now.\nDuring matcher creation mlx5dr code will process the match\ntemplates and check if such hash definer is needed based\non the definers bitmasks intersection.\nSince current HW GTA implementation doesn't allow specifying\nmatch and hash definers rule insertion is done using the FW\nGTA WQE command.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/common/mlx5/mlx5_prm.h | 4 +\n drivers/net/mlx5/hws/mlx5dr_definer.c | 105 ++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_matcher.c | 66 +++++++++++++++-\n drivers/net/mlx5/hws/mlx5dr_matcher.h | 10 ++-\n 4 files changed, 181 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 298cc48b06..243952bf85 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -2112,6 +2112,10 @@ enum mlx5_ifc_cross_vhca_allowed_objects_types {\n \tMLX5_CROSS_VHCA_ALLOWED_OBJS_RTC = 1 << 0xa,\n };\n \n+enum {\n+\tMLX5_GENERATE_WQE_TYPE_FLOW_UPDATE = 1 << 1,\n+};\n+\n /*\n * HCA Capabilities 2\n */\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 75e997ba28..0da38a818c 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -1928,6 +1928,27 @@ int mlx5dr_definer_get_id(struct mlx5dr_definer *definer)\n \treturn definer->obj->id;\n }\n \n+static int\n+mlx5dr_definer_compare(struct mlx5dr_definer *definer_a,\n+\t\t struct mlx5dr_definer *definer_b)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < BYTE_SELECTORS; i++)\n+\t\tif (definer_a->byte_selector[i] != definer_b->byte_selector[i])\n+\t\t\treturn 1;\n+\n+\tfor (i = 0; i < DW_SELECTORS; i++)\n+\t\tif (definer_a->dw_selector[i] != definer_b->dw_selector[i])\n+\t\t\treturn 1;\n+\n+\tfor (i = 0; i < MLX5DR_JUMBO_TAG_SZ; i++)\n+\t\tif (definer_a->mask.jumbo[i] != definer_b->mask.jumbo[i])\n+\t\t\treturn 1;\n+\n+\treturn 0;\n+}\n+\n static int\n mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher,\n \t\t\t struct mlx5dr_definer *match_definer)\n@@ -2070,6 +2091,80 @@ mlx5dr_definer_matcher_match_uninit(struct mlx5dr_matcher *matcher)\n \t\tmlx5dr_definer_free(matcher->mt[i].definer);\n }\n \n+static int\n+mlx5dr_definer_matcher_hash_init(struct mlx5dr_context *ctx,\n+\t\t\t\t struct mlx5dr_matcher *matcher)\n+{\n+\tstruct mlx5dr_cmd_definer_create_attr def_attr = {0};\n+\tstruct mlx5dr_match_template *mt = matcher->mt;\n+\tstruct ibv_context *ibv_ctx = ctx->ibv_ctx;\n+\tuint8_t *bit_mask;\n+\tint i, j;\n+\n+\tfor (i = 1; i < matcher->num_of_mt; i++)\n+\t\tif (mlx5dr_definer_compare(mt[i].definer, mt[i - 1].definer))\n+\t\t\tmatcher->flags |= MLX5DR_MATCHER_FLAGS_HASH_DEFINER;\n+\n+\tif (!(matcher->flags & MLX5DR_MATCHER_FLAGS_HASH_DEFINER))\n+\t\treturn 0;\n+\n+\t/* Insert by index requires all MT using the same definer */\n+\tif (matcher->attr.insert_mode == MLX5DR_MATCHER_INSERT_BY_INDEX) {\n+\t\tDR_LOG(ERR, \"Insert by index not supported with MT combination\");\n+\t\trte_errno = EOPNOTSUPP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tmatcher->hash_definer = simple_calloc(1, sizeof(*matcher->hash_definer));\n+\tif (!matcher->hash_definer) {\n+\t\tDR_LOG(ERR, \"Failed to allocate memory for hash definer\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn rte_errno;\n+\t}\n+\n+\t/* Calculate intersection between all match templates bitmasks.\n+\t * We will use mt[0] as reference and intersect it with mt[1..n].\n+\t * From this we will get:\n+\t * hash_definer.selectors = mt[0].selecotrs\n+\t * hash_definer.mask = mt[0].mask & mt[0].mask & ... & mt[n].mask\n+\t */\n+\n+\t/* Use first definer which should also contain intersection fields */\n+\tmemcpy(matcher->hash_definer, mt->definer, sizeof(struct mlx5dr_definer));\n+\n+\t/* Calculate intersection between first to all match templates bitmasks */\n+\tfor (i = 1; i < matcher->num_of_mt; i++) {\n+\t\tbit_mask = (uint8_t *)&mt[i].definer->mask;\n+\t\tfor (j = 0; j < MLX5DR_JUMBO_TAG_SZ; j++)\n+\t\t\t((uint8_t *)&matcher->hash_definer->mask)[j] &= bit_mask[j];\n+\t}\n+\n+\tdef_attr.match_mask = matcher->hash_definer->mask.jumbo;\n+\tdef_attr.dw_selector = matcher->hash_definer->dw_selector;\n+\tdef_attr.byte_selector = matcher->hash_definer->byte_selector;\n+\tmatcher->hash_definer->obj = mlx5dr_cmd_definer_create(ibv_ctx, &def_attr);\n+\tif (!matcher->hash_definer->obj) {\n+\t\tDR_LOG(ERR, \"Failed to create hash definer\");\n+\t\tgoto free_hash_definer;\n+\t}\n+\n+\treturn 0;\n+\n+free_hash_definer:\n+\tsimple_free(matcher->hash_definer);\n+\treturn rte_errno;\n+}\n+\n+static void\n+mlx5dr_definer_matcher_hash_uninit(struct mlx5dr_matcher *matcher)\n+{\n+\tif (!matcher->hash_definer)\n+\t\treturn;\n+\n+\tmlx5dr_cmd_destroy_obj(matcher->hash_definer->obj);\n+\tsimple_free(matcher->hash_definer);\n+}\n+\n int mlx5dr_definer_matcher_init(struct mlx5dr_context *ctx,\n \t\t\t\tstruct mlx5dr_matcher *matcher)\n {\n@@ -2093,8 +2188,17 @@ int mlx5dr_definer_matcher_init(struct mlx5dr_context *ctx,\n \t\tgoto free_fc;\n \t}\n \n+\t/* Calculate partial hash definer */\n+\tret = mlx5dr_definer_matcher_hash_init(ctx, matcher);\n+\tif (ret) {\n+\t\tDR_LOG(ERR, \"Failed to init hash definer\");\n+\t\tgoto uninit_match_definer;\n+\t}\n+\n \treturn 0;\n \n+uninit_match_definer:\n+\tmlx5dr_definer_matcher_match_uninit(matcher);\n free_fc:\n \tfor (i = 0; i < matcher->num_of_mt; i++)\n \t\tsimple_free(matcher->mt[i].fc);\n@@ -2109,6 +2213,7 @@ void mlx5dr_definer_matcher_uninit(struct mlx5dr_matcher *matcher)\n \tif (matcher->flags & MLX5DR_MATCHER_FLAGS_COLLISION)\n \t\treturn;\n \n+\tmlx5dr_definer_matcher_hash_uninit(matcher);\n \tmlx5dr_definer_matcher_match_uninit(matcher);\n \n \tfor (i = 0; i < matcher->num_of_mt; i++)\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.c b/drivers/net/mlx5/hws/mlx5dr_matcher.c\nindex 4334b87cef..0158a60ac3 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_matcher.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_matcher.c\n@@ -337,6 +337,42 @@ static int mlx5dr_matcher_disconnect(struct mlx5dr_matcher *matcher)\n \treturn 0;\n }\n \n+static bool mlx5dr_matcher_supp_fw_wqe(struct mlx5dr_matcher *matcher)\n+{\n+\tstruct mlx5dr_cmd_query_caps *caps = matcher->tbl->ctx->caps;\n+\n+\tif (matcher->flags & MLX5DR_MATCHER_FLAGS_HASH_DEFINER) {\n+\t\tif (matcher->hash_definer->type == MLX5DR_DEFINER_TYPE_MATCH &&\n+\t\t !IS_BIT_SET(caps->supp_ste_format_gen_wqe, MLX5_IFC_RTC_STE_FORMAT_8DW)) {\n+\t\t\tDR_LOG(ERR, \"Gen WQE MATCH format not supported\");\n+\t\t\treturn false;\n+\t\t}\n+\n+\t\tif (matcher->hash_definer->type == MLX5DR_DEFINER_TYPE_JUMBO) {\n+\t\t\tDR_LOG(ERR, \"Gen WQE JUMBO format not supported\");\n+\t\t\treturn false;\n+\t\t}\n+\t}\n+\n+\tif (matcher->attr.insert_mode != MLX5DR_MATCHER_INSERT_BY_HASH ||\n+\t matcher->attr.distribute_mode != MLX5DR_MATCHER_DISTRIBUTE_BY_HASH) {\n+\t\tDR_LOG(ERR, \"Gen WQE must be inserted and distribute by hash\");\n+\t\treturn false;\n+\t}\n+\n+\tif (!(caps->supp_type_gen_wqe & MLX5_GENERATE_WQE_TYPE_FLOW_UPDATE)) {\n+\t\tDR_LOG(ERR, \"Gen WQE command not supporting GTA\");\n+\t\treturn false;\n+\t}\n+\n+\tif (!caps->rtc_max_hash_def_gen_wqe) {\n+\t\tDR_LOG(ERR, \"Hash definer not supported\");\n+\t\treturn false;\n+\t}\n+\n+\treturn true;\n+}\n+\n static void mlx5dr_matcher_set_rtc_attr_sz(struct mlx5dr_matcher *matcher,\n \t\t\t\t\t struct mlx5dr_cmd_rtc_create_attr *rtc_attr,\n \t\t\t\t\t enum mlx5dr_matcher_rtc_type rtc_type,\n@@ -432,8 +468,16 @@ static int mlx5dr_matcher_create_rtc(struct mlx5dr_matcher *matcher,\n \t\tif (attr->insert_mode == MLX5DR_MATCHER_INSERT_BY_HASH) {\n \t\t\t/* The usual Hash Table */\n \t\t\trtc_attr.update_index_mode = MLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH;\n-\t\t\t/* The first match template is used since all share the same definer */\n-\t\t\trtc_attr.match_definer_0 = mlx5dr_definer_get_id(mt->definer);\n+\t\t\tif (matcher->hash_definer) {\n+\t\t\t\t/* Specify definer_id_0 is used for hashing */\n+\t\t\t\trtc_attr.fw_gen_wqe = true;\n+\t\t\t\trtc_attr.num_hash_definer = 1;\n+\t\t\t\trtc_attr.match_definer_0 =\n+\t\t\t\t\tmlx5dr_definer_get_id(matcher->hash_definer);\n+\t\t\t} else {\n+\t\t\t\t/* The first mt is used since all share the same definer */\n+\t\t\t\trtc_attr.match_definer_0 = mlx5dr_definer_get_id(mt->definer);\n+\t\t\t}\n \t\t} else if (attr->insert_mode == MLX5DR_MATCHER_INSERT_BY_INDEX) {\n \t\t\trtc_attr.update_index_mode = MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET;\n \t\t\trtc_attr.num_hash_definer = 1;\n@@ -640,6 +684,12 @@ static int mlx5dr_matcher_bind_at(struct mlx5dr_matcher *matcher)\n \tif (!matcher->action_ste.max_stes)\n \t\treturn 0;\n \n+\tif (mlx5dr_matcher_req_fw_wqe(matcher)) {\n+\t\tDR_LOG(ERR, \"FW extended matcher cannot be binded to complex at\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n \t/* Allocate action STE mempool */\n \tpool_attr.table_type = tbl->type;\n \tpool_attr.pool_type = MLX5DR_POOL_TYPE_STE;\n@@ -701,13 +751,21 @@ static int mlx5dr_matcher_bind_mt(struct mlx5dr_matcher *matcher)\n \tstruct mlx5dr_pool_attr pool_attr = {0};\n \tint ret;\n \n-\t/* Calculate match definers */\n+\t/* Calculate match and hash definers */\n \tret = mlx5dr_definer_matcher_init(ctx, matcher);\n \tif (ret) {\n \t\tDR_LOG(ERR, \"Failed to set matcher templates with match definers\");\n \t\treturn ret;\n \t}\n \n+\tif (mlx5dr_matcher_req_fw_wqe(matcher) &&\n+\t !mlx5dr_matcher_supp_fw_wqe(matcher)) {\n+\t\tDR_LOG(ERR, \"Matcher requires FW WQE which is not supported\");\n+\t\trte_errno = ENOTSUP;\n+\t\tret = rte_errno;\n+\t\tgoto uninit_match_definer;\n+\t}\n+\n \t/* Create an STE pool per matcher*/\n \tpool_attr.table_type = matcher->tbl->type;\n \tpool_attr.pool_type = MLX5DR_POOL_TYPE_STE;\n@@ -719,6 +777,7 @@ static int mlx5dr_matcher_bind_mt(struct mlx5dr_matcher *matcher)\n \tmatcher->match_ste.pool = mlx5dr_pool_create(ctx, &pool_attr);\n \tif (!matcher->match_ste.pool) {\n \t\tDR_LOG(ERR, \"Failed to allocate matcher STE pool\");\n+\t\tret = ENOTSUP;\n \t\tgoto uninit_match_definer;\n \t}\n \n@@ -932,6 +991,7 @@ mlx5dr_matcher_create_col_matcher(struct mlx5dr_matcher *matcher)\n \tcol_matcher->at = matcher->at;\n \tcol_matcher->num_of_at = matcher->num_of_at;\n \tcol_matcher->num_of_mt = matcher->num_of_mt;\n+\tcol_matcher->hash_definer = matcher->hash_definer;\n \tcol_matcher->attr.priority = matcher->attr.priority;\n \tcol_matcher->flags = matcher->flags;\n \tcol_matcher->flags |= MLX5DR_MATCHER_FLAGS_COLLISION;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.h b/drivers/net/mlx5/hws/mlx5dr_matcher.h\nindex fabf50a343..8dadc0ee66 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_matcher.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_matcher.h\n@@ -23,7 +23,8 @@\n #define MLX5DR_MATCHER_ASSURED_MAIN_TBL_DEPTH 2\n \n enum mlx5dr_matcher_flags {\n-\tMLX5DR_MATCHER_FLAGS_COLLISION\t\t= 1 << 0,\n+\tMLX5DR_MATCHER_FLAGS_HASH_DEFINER\t= 1 << 0,\n+\tMLX5DR_MATCHER_FLAGS_COLLISION\t\t= 1 << 1,\n };\n \n struct mlx5dr_match_template {\n@@ -69,6 +70,7 @@ struct mlx5dr_matcher {\n \tstruct mlx5dr_matcher *col_matcher;\n \tstruct mlx5dr_matcher_match_ste match_ste;\n \tstruct mlx5dr_matcher_action_ste action_ste;\n+\tstruct mlx5dr_definer *hash_definer;\n \tLIST_ENTRY(mlx5dr_matcher) next;\n };\n \n@@ -78,6 +80,12 @@ mlx5dr_matcher_mt_is_jumbo(struct mlx5dr_match_template *mt)\n \treturn mlx5dr_definer_is_jumbo(mt->definer);\n }\n \n+static inline bool mlx5dr_matcher_req_fw_wqe(struct mlx5dr_matcher *matcher)\n+{\n+\t/* Currently HWS doesn't support hash different from match or range */\n+\treturn unlikely(matcher->flags & MLX5DR_MATCHER_FLAGS_HASH_DEFINER);\n+}\n+\n int mlx5dr_matcher_conv_items_to_prm(uint64_t *match_buf,\n \t\t\t\t struct rte_flow_item *items,\n \t\t\t\t uint8_t *match_criteria,\n", "prefixes": [ "v2", "11/16" ] }