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GET /api/patches/126583/?format=api
{ "id": 126583, "url": "http://patchwork.dpdk.org/api/patches/126583/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20230427062001.478032-17-qiming.yang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20230427062001.478032-17-qiming.yang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20230427062001.478032-17-qiming.yang@intel.com", "date": "2023-04-27T06:19:47", "name": "[16/30] net/ice/base: add E830 PTP init", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6a94efd1fd73203e7e7e56cf0b56a41a400bc535", "submitter": { "id": 522, "url": "http://patchwork.dpdk.org/api/people/522/?format=api", "name": "Qiming Yang", "email": "qiming.yang@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20230427062001.478032-17-qiming.yang@intel.com/mbox/", "series": [ { "id": 27885, "url": "http://patchwork.dpdk.org/api/series/27885/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=27885", "date": "2023-04-27T06:19:31", "name": "net/ice/base: share code update", "version": 1, "mbox": "http://patchwork.dpdk.org/series/27885/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/126583/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/126583/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 38B5C42A08;\n\tThu, 27 Apr 2023 08:39:48 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2A66942F9C;\n\tThu, 27 Apr 2023 08:38:18 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 4907E42F88\n for <dev@dpdk.org>; Thu, 27 Apr 2023 08:38:15 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Apr 2023 23:38:14 -0700", "from dpdk-qiming3.sh.intel.com ([10.67.111.4])\n by fmsmga002.fm.intel.com with ESMTP; 26 Apr 2023 23:38:11 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1682577495; x=1714113495;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=nEdQAcbZbgaS5kRn7kpVvhaVVOVI0JaEDSGC+g0cELs=;\n b=aZo5LyXAjZuAwVihB71+zS3tsQvu0Y3b+RwI4CGoJFR/u+T9qTIak2lu\n uZRF73l0DAXfk8+lGJqSwcxvX+FpnkM7U4lhapF5qZyw9DDTbs7PapxsV\n UCink1l3xWut8R5W/WS0yLkIj4FZfyI0eUdJEpRxlBQEwCRzDDaH1Dmy6\n XKHVkFfpAgWBaxN3h/08DwCljAs5hCOJ5D+PYq1z6urbEGQdmkVViW60I\n Gna5+69W5GazmlfWSe2MMart9SN+o9+RbHiuExx2PPquBJL67dRIoPSpA\n RyKfqzwEBVD9DGctaHJfGECo61NpLgrlg9tt0qq/Q71Yz3udAJguYhIp2 Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10692\"; a=\"375324346\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"375324346\"", "E=McAfee;i=\"6600,9927,10692\"; a=\"805845817\"", "E=Sophos;i=\"5.99,230,1677571200\"; d=\"scan'208\";a=\"805845817\"" ], "X-ExtLoop1": "1", "From": "Qiming Yang <qiming.yang@intel.com>", "To": "dev@dpdk.org", "Cc": "qi.z.zhang@intel.com, Qiming Yang <qiming.yang@intel.com>,\n Paul Greenwalt <paul.greenwalt@intel.com>,\n Sergey Temerkhanov <sergey.temerkhanov@intel.com>", "Subject": "[PATCH 16/30] net/ice/base: add E830 PTP init", "Date": "Thu, 27 Apr 2023 06:19:47 +0000", "Message-Id": "<20230427062001.478032-17-qiming.yang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20230427062001.478032-1-qiming.yang@intel.com>", "References": "<20230427062001.478032-1-qiming.yang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The E830, E822 and E810 PTP initialization flows are similar. So\nrelated fix are also added.\n\nSigned-off-by: Paul Greenwalt <paul.greenwalt@intel.com>\nSigned-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>\nSigned-off-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_ptp_hw.c | 295 +++++++++++++++++++-----------\n drivers/net/ice/base/ice_ptp_hw.h | 94 +++++++++-\n drivers/net/ice/base/ice_type.h | 18 +-\n drivers/net/ice/ice_ethdev.c | 6 +-\n 4 files changed, 298 insertions(+), 115 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex 43b7e313f4..a638bb114c 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -448,6 +448,17 @@ static void ice_ptp_clean_cmd(struct ice_hw *hw)\n \tice_flush(hw);\n }\n \n+/**\n+ * ice_ptp_zero_syn_dlay - Set synchronization delay to zero\n+ * @hw: pointer to HW struct\n+ *\n+ * Zero E810 and E830 specific PTP hardware clock synchronization delay.\n+ */\n+static void ice_ptp_zero_syn_dlay(struct ice_hw *hw)\n+{\n+\twr32(hw, GLTSYN_SYNC_DLAY, 0);\n+\tice_flush(hw);\n+}\n \n /* ----------------------------------------------------------------------------\n * E822 family functions\n@@ -1037,6 +1048,33 @@ ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)\n \treturn ICE_SUCCESS;\n }\n \n+/**\n+ * ice_ptp_reset_ts_memory_quad_e822 - Clear all timestamps from the quad block\n+ * @hw: pointer to the HW struct\n+ * @quad: the quad to read from\n+ *\n+ * Clear all timestamps from the PHY quad block that is shared between the\n+ * internal PHYs on the E822 devices.\n+ */\n+void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad)\n+{\n+\tice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);\n+\tice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);\n+}\n+\n+/**\n+ * ice_ptp_reset_ts_memory_e822 - Clear all timestamps from all quad blocks\n+ * @hw: pointer to the HW struct\n+ */\n+static void ice_ptp_reset_ts_memory_e822(struct ice_hw *hw)\n+{\n+\tu8 quad;\n+\n+\tfor (quad = 0; quad < ICE_MAX_QUAD; quad++) {\n+\t\tice_ptp_reset_ts_memory_quad_e822(hw, quad);\n+\t}\n+}\n+\n /**\n * ice_ptp_set_vernier_wl - Set the window length for vernier calibration\n * @hw: pointer to the HW struct\n@@ -2652,89 +2690,43 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)\n }\n \n /**\n- * ice_phy_exit_bypass_e822 - Exit bypass mode, after vernier calculations\n+ * ice_get_phy_tx_tstamp_ready_e822 - Read Tx memory status register\n * @hw: pointer to the HW struct\n- * @port: the PHY port to configure\n- *\n- * After hardware finishes vernier calculations for the Tx and Rx offset, this\n- * function can be used to exit bypass mode by updating the total Tx and Rx\n- * offsets, and then disabling bypass. This will enable hardware to include\n- * the more precise offset calibrations, increasing precision of the generated\n- * timestamps.\n+ * @quad: the timestamp quad to read from\n+ * @tstamp_ready: contents of the Tx memory status register\n *\n- * This cannot be done until hardware has measured the offsets, which requires\n- * waiting until at least one packet has been sent and received by the device.\n+ * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in\n+ * the PHY are ready. A set bit means the corresponding timestamp is valid and\n+ * ready to be captured from the PHY timestamp block.\n */\n-enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port)\n+static enum ice_status\n+ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)\n {\n \tenum ice_status status;\n-\tu32 val;\n+\tu32 hi, lo;\n \n-\tstatus = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, &val);\n+\tstatus = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_U,\n+\t\t\t\t\t&hi);\n \tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read TX_OV_STATUS for port %u, status %d\\n\",\n-\t\t\t port, status);\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read TX_MEMORY_STATUS_U for quad %u, status %d\\n\",\n+\t\t\t quad, status);\n \t\treturn status;\n \t}\n \n-\tif (!(val & P_REG_TX_OV_STATUS_OV_M)) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Tx offset is not yet valid for port %u\\n\",\n-\t\t\t port);\n-\t\treturn ICE_ERR_NOT_READY;\n-\t}\n-\n-\tstatus = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, &val);\n+\tstatus = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_L,\n+\t\t\t\t\t&lo);\n \tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read RX_OV_STATUS for port %u, status %d\\n\",\n-\t\t\t port, status);\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read TX_MEMORY_STATUS_L for quad %u, status %d\\n\",\n+\t\t\t quad, status);\n \t\treturn status;\n \t}\n \n-\tif (!(val & P_REG_TX_OV_STATUS_OV_M)) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Rx offset is not yet valid for port %u\\n\",\n-\t\t\t port);\n-\t\treturn ICE_ERR_NOT_READY;\n-\t}\n-\n-\tstatus = ice_phy_cfg_tx_offset_e822(hw, port);\n-\tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to program total Tx offset for port %u, status %d\\n\",\n-\t\t\t port, status);\n-\t\treturn status;\n-\t}\n-\n-\tstatus = ice_phy_cfg_rx_offset_e822(hw, port);\n-\tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to program total Rx offset for port %u, status %d\\n\",\n-\t\t\t port, status);\n-\t\treturn status;\n-\t}\n-\n-\t/* Exit bypass mode now that the offset has been updated */\n-\tstatus = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);\n-\tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read P_REG_PS for port %u, status %d\\n\",\n-\t\t\t port, status);\n-\t\treturn status;\n-\t}\n-\n-\tif (!(val & P_REG_PS_BYPASS_MODE_M))\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Port %u not in bypass mode\\n\",\n-\t\t\t port);\n-\n-\tval &= ~P_REG_PS_BYPASS_MODE_M;\n-\tstatus = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);\n-\tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to disable bypass for port %u, status %d\\n\",\n-\t\t\t port, status);\n-\t\treturn status;\n-\t}\n-\n-\tice_info(hw, \"Exiting bypass mode on PHY port %u\\n\", port);\n+\t*tstamp_ready = (u64)hi << 32 | (u64)lo;\n \n \treturn ICE_SUCCESS;\n }\n \n+\n /* E810 functions\n *\n * The following functions operate on the E810 series devices which use\n@@ -3218,6 +3210,22 @@ ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,\n \treturn ICE_SUCCESS;\n }\n \n+/**\n+ * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register\n+ * @hw: pointer to the HW struct\n+ * @port: the PHY port to read\n+ * @tstamp_ready: contents of the Tx memory status register\n+ *\n+ * E810 devices do not use a Tx memory status register. Instead simply\n+ * indicate that all timestamps are currently ready.\n+ */\n+static enum ice_status\n+ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready)\n+{\n+\t*tstamp_ready = 0xFFFFFFFFFFFFFFFF;\n+\treturn ICE_SUCCESS;\n+}\n+\n /* E810T SMA functions\n *\n * The following functions operate specifically on E810T hardware and are used\n@@ -3445,6 +3453,23 @@ bool ice_is_pca9575_present(struct ice_hw *hw)\n \treturn false;\n }\n \n+/* E830 functions\n+ *\n+ * The following functions operate on the E830 series devices.\n+ *\n+ */\n+\n+/**\n+ * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization\n+ * @hw: pointer to HW struct\n+ *\n+ * Perform E830-specific PTP hardware clock initialization steps.\n+ */\n+static enum ice_status ice_ptp_init_phc_e830(struct ice_hw *hw)\n+{\n+\tice_ptp_zero_syn_dlay(hw);\n+\treturn ICE_SUCCESS;\n+}\n /* Device agnostic functions\n *\n * The following functions implement shared behavior common to both E822/E823\n@@ -3501,6 +3526,29 @@ void ice_ptp_unlock(struct ice_hw *hw)\n \twr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0);\n }\n \n+#define ICE_DEVID_MASK 0xFFF8\n+\n+/**\n+ * ice_ptp_init_phy_model - Initialize hw->phy_model based on device type\n+ * @hw: pointer to the HW structure\n+ *\n+ * Determine the PHY model for the device, and initialize hw->phy_model\n+ * for use by other functions.\n+ */\n+enum ice_status ice_ptp_init_phy_model(struct ice_hw *hw)\n+{\n+\n+\tif (ice_is_e810(hw))\n+\t\thw->phy_model = ICE_PHY_E810;\n+\telse if (ice_is_e830(hw))\n+\t\thw->phy_model = ICE_PHY_E830;\n+\telse\n+\t\thw->phy_model = ICE_PHY_E822;\n+\thw->phy_ports = ICE_NUM_EXTERNAL_PORTS;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n /**\n * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command\n * @hw: pointer to HW struct\n@@ -3521,16 +3569,20 @@ ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq)\n \tice_ptp_src_cmd(hw, cmd);\n \n \t/* Next, prepare the ports */\n-\tswitch (hw->phy_cfg) {\n+\tswitch (hw->phy_model) {\n \tcase ICE_PHY_E810:\n \t\tstatus = ice_ptp_port_cmd_e810(hw, cmd, lock_sbq);\n \t\tbreak;\n \tcase ICE_PHY_E822:\n \t\tstatus = ice_ptp_port_cmd_e822(hw, cmd, lock_sbq);\n \t\tbreak;\n+\tcase ICE_PHY_E830:\n+\t\tstatus = ICE_SUCCESS;\n+\t\tbreak;\n \tdefault:\n \t\tstatus = ICE_ERR_NOT_SUPPORTED;\n \t}\n+\n \tif (status) {\n \t\tice_debug(hw, ICE_DBG_PTP, \"Failed to prepare PHY ports for timer command %u, status %d\\n\",\n \t\t\t cmd, status);\n@@ -3577,13 +3629,16 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time,\n \n \t/* PHY Clks */\n \t/* Fill Rx and Tx ports and send msg to PHY */\n-\tswitch (hw->phy_cfg) {\n+\tswitch (hw->phy_model) {\n \tcase ICE_PHY_E810:\n \t\tstatus = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);\n \t\tbreak;\n \tcase ICE_PHY_E822:\n \t\tstatus = ice_ptp_prep_phy_time_e822(hw, time & 0xFFFFFFFF);\n \t\tbreak;\n+\tcase ICE_PHY_E830:\n+\t\tstatus = ICE_SUCCESS;\n+\t\tbreak;\n \tdefault:\n \t\tstatus = ICE_ERR_NOT_SUPPORTED;\n \t}\n@@ -3623,13 +3678,16 @@ enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval,\n \t\twr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval));\n \t}\n \n-\tswitch (hw->phy_cfg) {\n+\tswitch (hw->phy_model) {\n \tcase ICE_PHY_E810:\n \t\tstatus = ice_ptp_prep_phy_incval_e810(hw, incval);\n \t\tbreak;\n \tcase ICE_PHY_E822:\n \t\tstatus = ice_ptp_prep_phy_incval_e822(hw, incval);\n \t\tbreak;\n+\tcase ICE_PHY_E830:\n+\t\tstatus = ICE_SUCCESS;\n+\t\tbreak;\n \tdefault:\n \t\tstatus = ICE_ERR_NOT_SUPPORTED;\n \t}\n@@ -3693,7 +3751,7 @@ enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq)\n \twr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);\n \twr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);\n \n-\tswitch (hw->phy_cfg) {\n+\tswitch (hw->phy_model) {\n \tcase ICE_PHY_E810:\n \t\tstatus = ice_ptp_prep_phy_adj_e810(hw, adj, lock_sbq);\n \t\tbreak;\n@@ -3751,7 +3809,7 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)\n \twr32(hw, GLTSYN_SHTIME_H(tmr_idx), time_hi);\n \n \t/* Prepare PHY port adjustments */\n-\tswitch (hw->phy_cfg) {\n+\tswitch (hw->phy_model) {\n \tcase ICE_PHY_E810:\n \t\tstatus = ice_ptp_prep_phy_adj_e810(hw, adj, true);\n \t\tbreak;\n@@ -3766,7 +3824,7 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)\n \t\treturn status;\n \n \t/* Set target time for each PHY port */\n-\tswitch (hw->phy_cfg) {\n+\tswitch (hw->phy_model) {\n \tcase ICE_PHY_E810:\n \t\tstatus = ice_ptp_prep_phy_adj_target_e810(hw, time_lo);\n \t\tbreak;\n@@ -3797,49 +3855,58 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)\n enum ice_status\n ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)\n {\n-\tenum ice_status status;\n-\n-\tswitch (hw->phy_cfg) {\n+\tswitch (hw->phy_model) {\n \tcase ICE_PHY_E810:\n-\t\tstatus = ice_read_phy_tstamp_e810(hw, block, idx, tstamp);\n-\t\tbreak;\n+\t\treturn ice_read_phy_tstamp_e810(hw, block, idx, tstamp);\n \tcase ICE_PHY_E822:\n-\t\tstatus = ice_read_phy_tstamp_e822(hw, block, idx, tstamp);\n-\t\tbreak;\n+\t\treturn ice_read_phy_tstamp_e822(hw, block, idx, tstamp);\n \tdefault:\n-\t\tstatus = ICE_ERR_NOT_SUPPORTED;\n+\t\treturn ICE_ERR_NOT_SUPPORTED;\n \t}\n-\n-\treturn status;\n }\n \n /**\n- * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block\n+ * ice_clear_phy_tstamp - Drop a timestamp from the timestamp block\n * @hw: pointer to the HW struct\n * @block: the block to read from\n * @idx: the timestamp index to reset\n *\n- * Clear a timestamp, resetting its valid bit, from the timestamp block. For\n- * E822 devices, the block is the quad to clear from. For E810 devices, the\n- * block is the logical port to clear from.\n+ * Drop a timestamp from the timestamp block by reading it. This will reset\n+ * the memory status bit allowing the timestamp index to be reused. For E822\n+ * devices, the block is the quad to clear from. For E810 devices, the block\n+ * is the logical port to clear from.\n+ *\n+ * This function should only be called on a timestamp index whose valid bit\n+ * is set according to ice_get_phy_tx_tstamp_ready.\n */\n enum ice_status\n ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)\n {\n-\tenum ice_status status;\n-\n-\tswitch (hw->phy_cfg) {\n+\tswitch (hw->phy_model) {\n \tcase ICE_PHY_E810:\n-\t\tstatus = ice_clear_phy_tstamp_e810(hw, block, idx);\n-\t\tbreak;\n+\t\treturn ice_clear_phy_tstamp_e810(hw, block, idx);\n \tcase ICE_PHY_E822:\n-\t\tstatus = ice_clear_phy_tstamp_e822(hw, block, idx);\n-\t\tbreak;\n+\t\treturn ice_clear_phy_tstamp_e822(hw, block, idx);\n \tdefault:\n-\t\tstatus = ICE_ERR_NOT_SUPPORTED;\n+\t\treturn ICE_ERR_NOT_SUPPORTED;\n \t}\n+}\n \n-\treturn status;\n+/**\n+ * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks\n+ * @hw: pointer to the HW struct\n+ */\n+void ice_ptp_reset_ts_memory(struct ice_hw *hw)\n+{\n+\tswitch (hw->phy_model) {\n+\tcase ICE_PHY_E822:\n+\t\tice_ptp_reset_ts_memory_e822(hw);\n+\t\tbreak;\n+\tcase ICE_PHY_E810:\n+\tcase ICE_PHY_E830:\n+\tdefault:\n+\t\treturn;\n+\t}\n }\n \n /**\n@@ -3850,7 +3917,6 @@ ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)\n */\n enum ice_status ice_ptp_init_phc(struct ice_hw *hw)\n {\n-\tenum ice_status status;\n \tu8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;\n \n \t/* Enable source clocks */\n@@ -3859,16 +3925,41 @@ enum ice_status ice_ptp_init_phc(struct ice_hw *hw)\n \t/* Clear event status indications for auxiliary pins */\n \t(void)rd32(hw, GLTSYN_STAT(src_idx));\n \n-\tswitch (hw->phy_cfg) {\n+\tswitch (hw->phy_model) {\n \tcase ICE_PHY_E810:\n-\t\tstatus = ice_ptp_init_phc_e810(hw);\n-\t\tbreak;\n+\t\treturn ice_ptp_init_phc_e810(hw);\n \tcase ICE_PHY_E822:\n-\t\tstatus = ice_ptp_init_phc_e822(hw);\n-\t\tbreak;\n+\t\treturn ice_ptp_init_phc_e822(hw);\n+\tcase ICE_PHY_E830:\n+\t\treturn ice_ptp_init_phc_e830(hw);\n \tdefault:\n-\t\tstatus = ICE_ERR_NOT_SUPPORTED;\n+\t\treturn ICE_ERR_NOT_SUPPORTED;\n \t}\n+}\n \n-\treturn status;\n+/**\n+ * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication\n+ * @hw: pointer to the HW struct\n+ * @block: the timestamp block to check\n+ * @tstamp_ready: storage for the PHY Tx memory status information\n+ *\n+ * Check the PHY for Tx timestamp memory status. This reports a 64 bit value\n+ * which indicates which timestamps in the block may be captured. A set bit\n+ * means the timestamp can be read. An unset bit means the timestamp is not\n+ * ready and software should avoid reading the register.\n+ */\n+enum ice_status\n+ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready)\n+{\n+\tswitch (hw->phy_model) {\n+\tcase ICE_PHY_E810:\n+\t\treturn ice_get_phy_tx_tstamp_ready_e810(hw, block,\n+\t\t\t\t\t\t\ttstamp_ready);\n+\tcase ICE_PHY_E822:\n+\t\treturn ice_get_phy_tx_tstamp_ready_e822(hw, block,\n+\t\t\t\t\t\t\ttstamp_ready);\n+\t\tbreak;\n+\tdefault:\n+\t\treturn ICE_ERR_NOT_SUPPORTED;\n+\t}\n }\ndiff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h\nindex 48a30f1f4e..e25018a68f 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.h\n+++ b/drivers/net/ice/base/ice_ptp_hw.h\n@@ -41,6 +41,14 @@ enum ice_ptp_fec_mode {\n \tICE_PTP_FEC_MODE_RS_FEC\n };\n \n+/* Main timer mode */\n+enum ice_src_tmr_mode {\n+\tICE_SRC_TMR_MODE_NANOSECONDS,\n+\tICE_SRC_TMR_MODE_LOCKED,\n+\n+\tNUM_ICE_SRC_TMR_MODE\n+};\n+\n /**\n * struct ice_time_ref_info_e822\n * @pll_freq: Frequency of PLL that drives timer ticks in Hz\n@@ -123,7 +131,10 @@ extern const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD];\n /* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for\n * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.\n */\n-#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL\n+\n+#define ICE_E810_PLL_FREQ\t\t812500000\n+#define ICE_PTP_NOMINAL_INCVAL_E810\t0x13b13b13bULL\n+#define E810_OUT_PROP_DELAY_NS 1\n \n /* Device agnostic functions */\n u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);\n@@ -144,9 +155,13 @@ enum ice_status\n ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);\n enum ice_status\n ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);\n+void ice_ptp_reset_ts_memory(struct ice_hw *hw);\n enum ice_status ice_ptp_init_phc(struct ice_hw *hw);\n-\n+enum ice_status\n+ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);\n /* E822 family functions */\n+#define LOCKED_INCVAL_E822 0x100000000ULL\n+\n enum ice_status\n ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val);\n enum ice_status\n@@ -166,6 +181,7 @@ ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port,\n enum ice_status\n ice_ptp_one_port_cmd_e822(struct ice_hw *hw, u8 port,\n \t\t\t enum ice_ptp_tmr_cmd cmd, bool lock_sbq);\n+void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad);\n enum ice_status\n ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,\n \t\t enum ice_clk_src clk_src);\n@@ -236,9 +252,83 @@ enum ice_status ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);\n enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);\n bool ice_is_pca9575_present(struct ice_hw *hw);\n \n+/*\n+ * ice_is_e830\n+ * @hw: pointer to the hardware structure\n+ *\n+ * returns true if the device is E830 based, false if not.\n+ */\n+static inline bool ice_is_e830(struct ice_hw *hw)\n+{\n+\treturn hw->mac_type == ICE_MAC_E830;\n+}\n+\n void\n ice_ptp_process_cgu_err(struct ice_hw *hw, struct ice_rq_event_info *event);\n \n+enum ice_status ice_ptp_init_phy_model(struct ice_hw *hw);\n+\n+/**\n+ * ice_ptp_get_pll_freq - Get PLL frequency\n+ * @hw: Board private structure\n+ */\n+static inline u64\n+ice_ptp_get_pll_freq(struct ice_hw *hw)\n+{\n+\tswitch (hw->phy_model) {\n+\tcase ICE_PHY_E810:\n+\t\treturn ICE_E810_PLL_FREQ;\n+\tcase ICE_PHY_E822:\n+\t\treturn ice_e822_pll_freq(ice_e822_time_ref(hw));\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+}\n+\n+static inline u64\n+ice_prop_delay(struct ice_hw *hw)\n+{\n+\tswitch (hw->phy_model) {\n+\tcase ICE_PHY_E810:\n+\t\treturn E810_OUT_PROP_DELAY_NS;\n+\tcase ICE_PHY_E822:\n+\t\treturn ice_e822_pps_delay(ice_e822_time_ref(hw));\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+}\n+\n+static inline enum ice_time_ref_freq\n+ice_time_ref(struct ice_hw *hw)\n+{\n+\tswitch (hw->phy_model) {\n+\tcase ICE_PHY_E810:\n+\tcase ICE_PHY_E822:\n+\t\treturn ice_e822_time_ref(hw);\n+\tdefault:\n+\t\treturn ICE_TIME_REF_FREQ_INVALID;\n+\t}\n+}\n+\n+static inline u64\n+ice_get_base_incval(struct ice_hw *hw, enum ice_src_tmr_mode src_tmr_mode)\n+{\n+\tswitch (hw->phy_model) {\n+\n+\tcase ICE_PHY_E810:\n+\t\treturn ICE_PTP_NOMINAL_INCVAL_E810;\n+\tcase ICE_PHY_E822:\n+\t\tif (src_tmr_mode == ICE_SRC_TMR_MODE_NANOSECONDS &&\n+\t\t ice_e822_time_ref(hw) < NUM_ICE_TIME_REF_FREQ)\n+\t\t\treturn ice_e822_nominal_incval(ice_e822_time_ref(hw));\n+\t\telse\n+\t\t\treturn LOCKED_INCVAL_E822;\n+\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+}\n \n #define PFTSYN_SEM_BYTES\t4\n \ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 576998549e..d072b0bfe2 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -760,7 +760,9 @@ enum ice_time_ref_freq {\n \tICE_TIME_REF_FREQ_156_250\t= 4,\n \tICE_TIME_REF_FREQ_245_760\t= 5,\n \n-\tNUM_ICE_TIME_REF_FREQ\n+\tNUM_ICE_TIME_REF_FREQ,\n+\n+\tICE_TIME_REF_FREQ_INVALID\t= -1,\n };\n \n /* Clock source specification */\n@@ -1246,11 +1248,12 @@ struct ice_switch_info {\n \tice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);\n };\n \n-/* PHY configuration */\n-enum ice_phy_cfg {\n-\tICE_PHY_E810 = 1,\n+/* PHY model */\n+enum ice_phy_model {\n+\tICE_PHY_UNSUP = -1,\n+\tICE_PHY_E810 = 1,\n \tICE_PHY_E822,\n-\tICE_PHY_ETH56G,\n+\tICE_PHY_E830,\n };\n \n /* Port hardware description */\n@@ -1277,7 +1280,8 @@ struct ice_hw {\n \tu8 revision_id;\n \n \tu8 pf_id;\t\t/* device profile info */\n-\tenum ice_phy_cfg phy_cfg;\n+\tenum ice_phy_model phy_model;\n+\tu8 phy_ports;\n \tu8 logical_pf_id;\n \n \tu16 max_burst_size;\t/* driver sets this value */\n@@ -1311,7 +1315,6 @@ struct ice_hw {\n \t\t\t void *buf, u16 buf_size);\n \tvoid *aq_send_cmd_param;\n \tu8 dcf_enabled;\t\t/* Device Config Function */\n-\n \tu8 api_branch;\t\t/* API branch version */\n \tu8 api_maj_ver;\t\t/* API major version */\n \tu8 api_min_ver;\t\t/* API minor version */\n@@ -1665,7 +1668,6 @@ struct ice_aq_get_set_rss_lut_params {\n /* AQ API version for report default configuration */\n #define ICE_FW_API_REPORT_DFLT_CFG_MAJ\t\t1\n #define ICE_FW_API_REPORT_DFLT_CFG_MIN\t\t7\n-\n #define ICE_FW_API_REPORT_DFLT_CFG_PATCH\t3\n \n /* FW version for FEC disable in Auto FEC mode */\ndiff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex 6700893bc5..a5bf8317a7 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -2414,11 +2414,11 @@ ice_dev_init(struct rte_eth_dev *dev)\n \tice_tm_conf_init(dev);\n \n \tif (ice_is_e810(hw))\n-\t\thw->phy_cfg = ICE_PHY_E810;\n+\t\thw->phy_model = ICE_PHY_E810;\n \telse\n-\t\thw->phy_cfg = ICE_PHY_E822;\n+\t\thw->phy_model = ICE_PHY_E822;\n \n-\tif (hw->phy_cfg == ICE_PHY_E822) {\n+\tif (hw->phy_model == ICE_PHY_E822) {\n \t\tret = ice_start_phy_timer_e822(hw, hw->pf_id, true);\n \t\tif (ret)\n \t\t\tPMD_INIT_LOG(ERR, \"Failed to start phy timer\\n\");\n", "prefixes": [ "16/30" ] }