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GET /api/patches/135755/?format=api
{ "id": 135755, "url": "http://patchwork.dpdk.org/api/patches/135755/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240105113250.11492-1-venkatkumar.ande@amd.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240105113250.11492-1-venkatkumar.ande@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240105113250.11492-1-venkatkumar.ande@amd.com", "date": "2024-01-05T11:32:50", "name": "[v1] net/axgbe: read and save the port property register", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "c5d99bc577abed606f47a5bcf8c395e2d5f8c379", "submitter": { "id": 3256, "url": "http://patchwork.dpdk.org/api/people/3256/?format=api", "name": "Venkat Kumar Ande", "email": "venkatkumar.ande@amd.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240105113250.11492-1-venkatkumar.ande@amd.com/mbox/", "series": [ { "id": 30739, "url": "http://patchwork.dpdk.org/api/series/30739/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30739", "date": "2024-01-05T11:32:50", "name": "[v1] net/axgbe: read and save the port property register", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30739/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/135755/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/135755/checks/", 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SFS:(13230031)(4636009)(376002)(346002)(39860400002)(396003)(136003)(230922051799003)(64100799003)(82310400011)(451199024)(1800799012)(186009)(46966006)(40470700004)(36840700001)(82740400003)(70206006)(70586007)(6916009)(47076005)(81166007)(356005)(7696005)(86362001)(6666004)(1076003)(2616005)(426003)(16526019)(336012)(26005)(5660300002)(2906002)(36756003)(478600001)(83380400001)(54906003)(316002)(8936002)(8676002)(4326008)(40460700003)(40480700001)(36860700001)(41300700001)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 Jan 2024 11:33:50.5209 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f2c057f0-f0eb-459b-0c2c-08dc0de2306d", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF0002BA4F.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4862", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Venkat Kumar Ande <VenkatKumar.Ande@amd.com>\n\nRead and save the port property registers once during the device probe\nand then use the saved values as they are needed.\n\nSigned-off-by: Venkat Kumar Ande <VenkatKumar.Ande@amd.com>\n---\n drivers/net/axgbe/axgbe_ethdev.c | 21 +++++----\n drivers/net/axgbe/axgbe_ethdev.h | 7 +++\n drivers/net/axgbe/axgbe_phy_impl.c | 68 ++++++++++++------------------\n 3 files changed, 48 insertions(+), 48 deletions(-)", "diff": "diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c\nindex f174d46143..3450374535 100644\n--- a/drivers/net/axgbe/axgbe_ethdev.c\n+++ b/drivers/net/axgbe/axgbe_ethdev.c\n@@ -2342,23 +2342,28 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev)\n \tpdata->arcache = AXGBE_DMA_OS_ARCACHE;\n \tpdata->awcache = AXGBE_DMA_OS_AWCACHE;\n \n+\t/* Read the port property registers */\n+\tpdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);\n+\tpdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);\n+\tpdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);\n+\tpdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);\n+\tpdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);\n+\n \t/* Set the maximum channels and queues */\n-\treg = XP_IOREAD(pdata, XP_PROP_1);\n-\tpdata->tx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_DMA);\n-\tpdata->rx_max_channel_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_DMA);\n-\tpdata->tx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_TX_QUEUES);\n-\tpdata->rx_max_q_count = XP_GET_BITS(reg, XP_PROP_1, MAX_RX_QUEUES);\n+\tpdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_TX_DMA);\n+\tpdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_RX_DMA);\n+\tpdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_TX_QUEUES);\n+\tpdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1, MAX_RX_QUEUES);\n \n \t/* Set the hardware channel and queue counts */\n \taxgbe_set_counts(pdata);\n \n \t/* Set the maximum fifo amounts */\n-\treg = XP_IOREAD(pdata, XP_PROP_2);\n-\tpdata->tx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, TX_FIFO_SIZE);\n+\tpdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2, TX_FIFO_SIZE);\n \tpdata->tx_max_fifo_size *= 16384;\n \tpdata->tx_max_fifo_size = RTE_MIN(pdata->tx_max_fifo_size,\n \t\t\t\t\t pdata->vdata->tx_max_fifo_size);\n-\tpdata->rx_max_fifo_size = XP_GET_BITS(reg, XP_PROP_2, RX_FIFO_SIZE);\n+\tpdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2, RX_FIFO_SIZE);\n \tpdata->rx_max_fifo_size *= 16384;\n \tpdata->rx_max_fifo_size = RTE_MIN(pdata->rx_max_fifo_size,\n \t\t\t\t\t pdata->vdata->rx_max_fifo_size);\ndiff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h\nindex 7f19321d88..df5d63c493 100644\n--- a/drivers/net/axgbe/axgbe_ethdev.h\n+++ b/drivers/net/axgbe/axgbe_ethdev.h\n@@ -539,6 +539,13 @@ struct axgbe_port {\n \tvoid *xprop_regs;\t/* AXGBE property registers */\n \tvoid *xi2c_regs;\t/* AXGBE I2C CSRs */\n \n+\t/* Port property registers */\n+\tunsigned int pp0;\n+\tunsigned int pp1;\n+\tunsigned int pp2;\n+\tunsigned int pp3;\n+\tunsigned int pp4;\n+\n \tbool cdr_track_early;\n \t/* XPCS indirect addressing lock */\n \tunsigned int xpcs_window_def_reg;\ndiff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c\nindex d97fbbfddd..44ff28517c 100644\n--- a/drivers/net/axgbe/axgbe_phy_impl.c\n+++ b/drivers/net/axgbe/axgbe_phy_impl.c\n@@ -1709,40 +1709,35 @@ static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart)\n static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata)\n {\n \tstruct axgbe_phy_data *phy_data = pdata->phy_data;\n-\tunsigned int reg;\n-\n-\treg = XP_IOREAD(pdata, XP_PROP_3);\n \n \tphy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 +\n-\t\tXP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR);\n+\t\tXP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_ADDR);\n \n-\tphy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK);\n+\tphy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_MASK);\n \n-\tphy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3,\n+\tphy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,\n \t\t\t\t\t\tGPIO_RX_LOS);\n-\tphy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3,\n+\tphy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,\n \t\t\t\t\t\t GPIO_TX_FAULT);\n-\tphy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3,\n+\tphy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,\n \t\t\t\t\t\t GPIO_MOD_ABS);\n-\tphy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3,\n+\tphy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,\n \t\t\t\t\t\t GPIO_RATE_SELECT);\n }\n \n static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata)\n {\n \tstruct axgbe_phy_data *phy_data = pdata->phy_data;\n-\tunsigned int reg, mux_addr_hi, mux_addr_lo;\n+\tunsigned int mux_addr_hi, mux_addr_lo;\n \n-\treg = XP_IOREAD(pdata, XP_PROP_4);\n-\n-\tmux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI);\n-\tmux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO);\n+\tmux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);\n+\tmux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);\n \tif (mux_addr_lo == AXGBE_SFP_DIRECT)\n \t\treturn;\n \n \tphy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545;\n \tphy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;\n-\tphy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN);\n+\tphy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_CHAN);\n }\n \n static void axgbe_phy_sfp_setup(struct axgbe_port *pdata)\n@@ -1778,12 +1773,11 @@ static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data)\n static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata)\n {\n \tstruct axgbe_phy_data *phy_data = pdata->phy_data;\n-\tunsigned int reg;\n \n \tif (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO)\n \t\treturn 0;\n-\treg = XP_IOREAD(pdata, XP_PROP_3);\n-\tphy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET);\n+\n+\tphy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);\n \tswitch (phy_data->mdio_reset) {\n \tcase AXGBE_MDIO_RESET_NONE:\n \tcase AXGBE_MDIO_RESET_I2C_GPIO:\n@@ -1796,12 +1790,12 @@ static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata)\n \t}\n \tif (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) {\n \t\tphy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 +\n-\t\t\tXP_GET_BITS(reg, XP_PROP_3,\n+\t\t\tXP_GET_BITS(pdata->pp3, XP_PROP_3,\n \t\t\t\t MDIO_RESET_I2C_ADDR);\n-\t\tphy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,\n+\t\tphy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,\n \t\t\t\t\t\t\tMDIO_RESET_I2C_GPIO);\n \t} else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) {\n-\t\tphy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3,\n+\t\tphy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,\n \t\t\t\t\t\t\tMDIO_RESET_INT_GPIO);\n \t}\n \n@@ -1893,12 +1887,9 @@ static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata)\n \n static bool axgbe_phy_port_enabled(struct axgbe_port *pdata)\n {\n-\tunsigned int reg;\n-\n-\treg = XP_IOREAD(pdata, XP_PROP_0);\n-\tif (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS))\n+\tif (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))\n \t\treturn false;\n-\tif (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE))\n+\tif (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))\n \t\treturn false;\n \n \treturn true;\n@@ -2061,7 +2052,6 @@ static int axgbe_phy_reset(struct axgbe_port *pdata)\n static int axgbe_phy_init(struct axgbe_port *pdata)\n {\n \tstruct axgbe_phy_data *phy_data;\n-\tunsigned int reg;\n \tint ret;\n \n \t/* Check if enabled */\n@@ -2082,19 +2072,17 @@ static int axgbe_phy_init(struct axgbe_port *pdata)\n \t}\n \tpdata->phy_data = phy_data;\n \n-\treg = XP_IOREAD(pdata, XP_PROP_0);\n-\tphy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE);\n-\tphy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID);\n-\tphy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS);\n-\tphy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE);\n-\tphy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR);\n-\n-\treg = XP_IOREAD(pdata, XP_PROP_4);\n-\tphy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT);\n-\tphy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF);\n-\tphy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR);\n-\tphy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE);\n-\tphy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL);\n+\tphy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);\n+\tphy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);\n+\tphy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);\n+\tphy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);\n+\tphy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);\n+\n+\tphy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);\n+\tphy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);\n+\tphy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);\n+\tphy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);\n+\tphy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);\n \n \t/* Validate the connection requested */\n \tif (axgbe_phy_conn_type_mismatch(pdata)) {\n", "prefixes": [ "v1" ] }