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GET /api/patches/135847/?format=api
{ "id": 135847, "url": "http://patchwork.dpdk.org/api/patches/135847/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240112075055.1288263-2-gavinl@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240112075055.1288263-2-gavinl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240112075055.1288263-2-gavinl@nvidia.com", "date": "2024-01-12T07:50:54", "name": "[V1,1/2] net/mlx5: discover IPv6 traffic class support in RDMA core", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6071b4a05320fd1aa78e741d3844538c964ec840", "submitter": { "id": 3217, "url": "http://patchwork.dpdk.org/api/people/3217/?format=api", "name": "Gavin Li", "email": "gavinl@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240112075055.1288263-2-gavinl@nvidia.com/mbox/", "series": [ { "id": 30787, "url": "http://patchwork.dpdk.org/api/series/30787/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30787", "date": "2024-01-12T07:50:53", "name": "use traffic class PRM field for IPv6 modification", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30787/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/135847/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/135847/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5E4984389F;\n\tFri, 12 Jan 2024 08:51:33 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4CCC84064E;\n\tFri, 12 Jan 2024 08:51:33 +0100 (CET)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2064.outbound.protection.outlook.com [40.107.220.64])\n by mails.dpdk.org (Postfix) with ESMTP id 5A3E44064A\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Gavin Li <gavinl@nvidia.com>", "To": "<dev@dpdk.org>, <dsosnowski@nvidia.com>, <viacheslavo@nvidia.com>,\n <orika@nvidia.com>, <suanmingm@nvidia.com>, <matan@nvidia.com>", "CC": "<jiaweiw@nvidia.com>, <rasland@nvidia.com>", "Subject": "[V1 1/2] net/mlx5: discover IPv6 traffic class support in RDMA core", "Date": "Fri, 12 Jan 2024 09:50:54 +0200", "Message-ID": "<20240112075055.1288263-2-gavinl@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240112075055.1288263-1-gavinl@nvidia.com>", "References": "<20240112075055.1288263-1-gavinl@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1PEPF000044FA:EE_|DM4PR12MB6256:EE_", "X-MS-Office365-Filtering-Correlation-Id": "6cc726b9-edc0-4fe2-94e2-08dc13434950", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 6oy4ci3wuzXkn4569IGzdPDBeU/Zcz7fkC9J8gYUg6k7yvF2wWY24J8FoXLXaCSaD9/p2abssJ/c7mFq3j2CBmB1GrCSE3tod3kyot2WeoKirtpiCULRiFLY7S3AX58dusxtOKd8vqDYk2Ign6yB27EZPavNJ66JFXcj/XPBRonC4ToqE2mIXeCKxB4tCbzuTYsgEtgBfu10ChwwC+jNpQSvB/L8vyZh4r3fiUw6igFB1BqnP2CNmryOBhOHRH//N6NwYOuHHi5cYBkNitnSN/rLMOQX5I3Z9uu5dX04j8lR8VQ2sOzw9N7o24WzMZgvPsWksiMKgobukhzNEO/sjAPVhdQPj0CUbkkxRh+lJih/f8Y+I5HzQGudGIIFsFOa93bmbp6LZ2d0etm2lUesUYWjFgLWbqOXyAQ2KY3KHBXJfGtBZPHyZuiKVVUk3ytmvzD4nZ7rz4zeVPYyFT/0LxfIfrCu9xkunpIZjR9I6sa0n/n7/UEqSlm1FhYCwqVRwVTT1NfDhp4HvM2/XhmAhsfv/vE96ZzUpdOugaMak+g2XECJZvGeK/K9Wvx+V2OEQFCJ3DkJ5+Hc8fH0quQpFm7hHU0dNg7kAFO1kymTZODJJhADRVv7JeMOntVtnQRq40mFoJT2lN1qcpVXElMK7+lvNIOYY9TvZNmqwt9Ju4l1YWnuj0DjuZvZU5GA5OHyVKrN+5j+Bz9aFHwWj0/GHzOy/uXWwejJPESAnTdQDLtafV3KQsz9RFOyzer8FGnu/HUE6Ra0fiXGIbrgx4C4GA==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(1800799012)(186009)(64100799003)(82310400011)(451199024)(40470700004)(46966006)(36840700001)(2616005)(16526019)(83380400001)(336012)(26005)(1076003)(426003)(110136005)(70206006)(107886003)(6666004)(36860700001)(6286002)(5660300002)(8676002)(478600001)(7696005)(2906002)(54906003)(4326008)(8936002)(6636002)(316002)(41300700001)(70586007)(7636003)(47076005)(82740400003)(86362001)(36756003)(356005)(40480700001)(40460700003)(55016003)(2101003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "12 Jan 2024 07:51:29.1959 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6cc726b9-edc0-4fe2-94e2-08dc13434950", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1PEPF000044FA.namprd21.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB6256", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Previously, IPv6 traffic class used the same ids of IPv4 DSCP and ECN by\nrdam core and firmware. New FW support new IPv6 traffic class id which is\nrecommended to be used though the old way is still working.\n\nFW exposed a new cap bit to indicate the supporting of the new id while\nRDMA core does not have such mechanism.\n\nTo fix the backward compatibility issue of combination of RDMA core and FW\nof different versions, a new function and a new flag were introduced to\ncheck if the new IPv6 traffic class id is supported by RDMA core.\n\nSigned-off-by: Gavin Li <gavinl@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 4 +++\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_flow.c | 42 ++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow.h | 1 +\n 4 files changed, 48 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex ae82e1e5d8..5ae31c88f4 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1602,6 +1602,10 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\tgoto error;\n \t}\n \trte_rwlock_init(&priv->ind_tbls_lock);\n+\tif (sh->config.dv_flow_en == 1 &&\n+\t !priv->sh->ipv6_tc_fallback &&\n+\t mlx5_flow_discover_ipv6_tc_support(eth_dev))\n+\t\tpriv->sh->ipv6_tc_fallback = 1;\n \tif (priv->sh->config.dv_flow_en == 2) {\n #ifdef HAVE_MLX5_HWS_SUPPORT\n \t\tif (priv->sh->config.dv_esw_en) {\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 263ebead7f..779805bcd8 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1444,6 +1444,7 @@ struct mlx5_dev_ctx_shared {\n \tuint32_t lag_rx_port_affinity_en:1;\n \t/* lag_rx_port_affinity is supported. */\n \tuint32_t hws_max_log_bulk_sz:5;\n+\tuint32_t ipv6_tc_fallback:1;\n \t/* Log of minimal HWS counters created hard coded. */\n \tuint32_t hws_max_nb_counters; /* Maximal number for HWS counters. */\n \tuint32_t max_port; /* Maximal IB device port index. */\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex 85e8c77c81..90b72b7b0a 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -12476,3 +12476,45 @@ mlx5_flow_pick_transfer_proxy(struct rte_eth_dev *dev,\n \t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED,\n \t\t\t\t NULL, \"unable to find a proxy port\");\n }\n+\n+/**\n+ * Discover ipv6 traffic class id support in rdma core and firmware.\n+ *\n+ * @param dev\n+ * Ethernet device.\n+ *\n+ * @return\n+ * 0, rdma core is good to work with firmware.\n+ * -EOPNOTSUPP, rdma core could not work with new ipv6 tc id.\n+ */\n+int\n+mlx5_flow_discover_ipv6_tc_support(struct rte_eth_dev *dev)\n+{\n+\tstruct rte_flow_action_set_dscp set_dscp;\n+\tstruct rte_flow_attr attr;\n+\tstruct rte_flow_action actions[2];\n+\tstruct rte_flow_item items[3];\n+\tstruct rte_flow_error error;\n+\tuint32_t flow_idx;\n+\n+\tmemset(&attr, 0, sizeof(attr));\n+\tmemset(actions, 0, sizeof(actions));\n+\tmemset(items, 0, sizeof(items));\n+\tattr.group = 1;\n+\tattr.egress = 1;\n+\titems[0].type = RTE_FLOW_ITEM_TYPE_ETH;\n+\titems[1].type = RTE_FLOW_ITEM_TYPE_IPV6;\n+\titems[2].type = RTE_FLOW_ITEM_TYPE_END;\n+\t/* Random value */\n+\tset_dscp.dscp = 9;\n+\tactions[0].type = RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP;\n+\tactions[0].conf = &set_dscp;\n+\tactions[1].type = RTE_FLOW_ACTION_TYPE_END;\n+\n+\tflow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, &attr, items, actions, true, &error);\n+\tif (!flow_idx)\n+\t\treturn -EOPNOTSUPP;\n+\n+\tflow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, flow_idx);\n+\treturn 0;\n+}\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 120609c595..33d4a28077 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -2638,6 +2638,7 @@ void mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,\n \t\tstruct mlx5_flow_meter_policy *mtr_policy);\n int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);\n int mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev);\n+int mlx5_flow_discover_ipv6_tc_support(struct rte_eth_dev *dev);\n int mlx5_action_handle_attach(struct rte_eth_dev *dev);\n int mlx5_action_handle_detach(struct rte_eth_dev *dev);\n int mlx5_action_handle_flush(struct rte_eth_dev *dev);\n", "prefixes": [ "V1", "1/2" ] }