[13/13] net/mlx5/hws: fix port ID for root matcher and rule

Message ID 20240314114220.203241-13-igozlan@nvidia.com (mailing list archive)
State Superseded
Delegated to: Raslan Darawsheh
Headers
Series [01/13] net/mlx5/hws: move warn into debug level when needed |

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Commit Message

Itamar Gozlan March 14, 2024, 11:42 a.m. UTC
  From: Erez Shitrit <erezsh@nvidia.com>

In root tables matcher and rule need to have their port-id, otherwise
the translate function that done in dpdk layer will not get the right
attributes.
For that whenever the matcher is matching the source-port we need to get
the relevant port-id before calling the translate function.

Fixes: 405242c52dd5 ("net/mlx5/hws: add rule object")
Signed-off-by: Erez Shitrit <erezsh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_matcher.c | 17 +++++++++++++++++
 drivers/net/mlx5/hws/mlx5dr_rule.c    | 18 ++++++++++++++++++
 drivers/net/mlx5/mlx5_flow.h          | 18 ++++++++++++++++++
 3 files changed, 53 insertions(+)
  

Patch

diff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.c b/drivers/net/mlx5/hws/mlx5dr_matcher.c
index 78d525e578..394244b55b 100644
--- a/drivers/net/mlx5/hws/mlx5dr_matcher.c
+++ b/drivers/net/mlx5/hws/mlx5dr_matcher.c
@@ -1227,6 +1227,7 @@  static int mlx5dr_matcher_init_root(struct mlx5dr_matcher *matcher)
 	struct mlx5dv_flow_match_parameters *mask;
 	struct mlx5_flow_attr flow_attr = {0};
 	struct rte_flow_error rte_error;
+	struct rte_flow_item *item;
 	uint8_t match_criteria;
 	int ret;
 
@@ -1255,6 +1256,22 @@  static int mlx5dr_matcher_init_root(struct mlx5dr_matcher *matcher)
 		return rte_errno;
 	}
 
+	/* We need the port id in case of matching representor */
+	item = matcher->mt[0].items;
+	while (item->type != RTE_FLOW_ITEM_TYPE_END) {
+		if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR ||
+		    item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) {
+			ret = flow_hw_get_port_id_from_ctx(ctx, &flow_attr.port_id);
+			if (ret) {
+				DR_LOG(ERR, "Failed to get port id for dev %s",
+				       ctx->ibv_ctx->device->name);
+				rte_errno = EINVAL;
+				return rte_errno;
+			}
+		}
+		++item;
+	}
+
 	mask = simple_calloc(1, MLX5_ST_SZ_BYTES(fte_match_param) +
 			     offsetof(struct mlx5dv_flow_match_parameters, match_buf));
 	if (!mask) {
diff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c
index d56677a1a5..5dae4f3442 100644
--- a/drivers/net/mlx5/hws/mlx5dr_rule.c
+++ b/drivers/net/mlx5/hws/mlx5dr_rule.c
@@ -692,10 +692,28 @@  static int mlx5dr_rule_create_root(struct mlx5dr_rule *rule,
 	struct mlx5dv_flow_match_parameters *value;
 	struct mlx5_flow_attr flow_attr = {0};
 	struct mlx5dv_flow_action_attr *attr;
+	const struct rte_flow_item *cur_item;
 	struct rte_flow_error error;
 	uint8_t match_criteria;
 	int ret;
 
+	/* We need the port id in case of matching representor */
+	cur_item = items;
+	while (cur_item->type != RTE_FLOW_ITEM_TYPE_END) {
+		if (cur_item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR ||
+		    cur_item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) {
+			ret = flow_hw_get_port_id_from_ctx(rule->matcher->tbl->ctx,
+							   &flow_attr.port_id);
+			if (ret) {
+				DR_LOG(ERR, "Failed to get port id for dev %s",
+				       rule->matcher->tbl->ctx->ibv_ctx->device->name);
+				rte_errno = EINVAL;
+				return rte_errno;
+			}
+		}
+		++cur_item;
+	}
+
 	attr = simple_calloc(num_actions, sizeof(*attr));
 	if (!attr) {
 		rte_errno = ENOMEM;
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 34b5e0f45b..e435a686fd 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -2001,6 +2001,24 @@  flow_hw_get_reg_id(struct rte_eth_dev *dev,
 #endif
 }
 
+static __rte_always_inline int
+flow_hw_get_port_id_from_ctx(void *dr_ctx, uint32_t *port_val)
+{
+	uint32_t port;
+
+	MLX5_ETH_FOREACH_DEV(port, NULL) {
+		struct mlx5_priv *priv;
+		priv = rte_eth_devices[port].data->dev_private;
+
+		if (priv->dr_ctx == dr_ctx) {
+			*port_val = port;
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
 /**
  * Get GENEVE TLV option FW information according type and class.
  *