diff mbox series

net/igc: fix memory illegal accesses

Message ID 20200507020133.14412-1-alvinx.zhang@intel.com (mailing list archive)
State Superseded, archived
Delegated to: xiaolong ye
Headers
Series net/igc: fix memory illegal accesses |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-nxp-Performance success Performance Testing PASS
ci/travis-robot success Travis build: passed
ci/Intel-compilation fail Compilation issues
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-testing fail Testing issues

Commit Message

Alvin Zhang May 7, 2020, 2:01 a.m. UTC 
  From: Alvin Zhang <alvinx.zhang@intel.com>

Add memory access out-of-bounds check.

Fixes: bd3fcf0d0fa1 (net/igc: support RSS)
Cc: stable@dpdk.org

Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
---
 drivers/net/igc/igc_ethdev.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

Comments

Guo, Jia May 7, 2020, 6:30 a.m. UTC | #1 
hi, alvin


On 5/7/2020 10:01 AM, alvinx.zhang@intel.com wrote:
> From: Alvin Zhang <alvinx.zhang@intel.com>
>
> Add memory access out-of-bounds check.


Could you explain why add ...?  If not add, what issue?


>
> Fixes: bd3fcf0d0fa1 (net/igc: support RSS)
> Cc: stable@dpdk.org
>
> Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
> ---
>   drivers/net/igc/igc_ethdev.c | 12 ++++++++++--
>   1 file changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/igc/igc_ethdev.c b/drivers/net/igc/igc_ethdev.c
> index 16d98c6..ced8ffd 100644
> --- a/drivers/net/igc/igc_ethdev.c
> +++ b/drivers/net/igc/igc_ethdev.c
> @@ -2266,6 +2266,8 @@ static int eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
>   		return -EINVAL;
>   	}
>   
> +	RTE_BUILD_BUG_ON(ETH_RSS_RETA_SIZE_128 % IGC_RSS_RDT_REG_SIZE);
> +
>   	/* set redirection table */
>   	for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE) {
>   		union igc_rss_reta_reg reta, reg;
> @@ -2278,7 +2280,8 @@ static int eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
>   				IGC_RSS_RDT_REG_SIZE_MASK);
>   
>   		/* if no need to update the register */
> -		if (!mask)
> +		if (!mask ||
> +			shift > (RTE_RETA_GROUP_SIZE - IGC_RSS_RDT_REG_SIZE))


alignment should be match above parentheses.


>   			continue;
>   
>   		/* check mask whether need to read the register value first */
> @@ -2289,6 +2292,7 @@ static int eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
>   					IGC_RETA(i / IGC_RSS_RDT_REG_SIZE));
>   
>   		/* update the register */
> +		RTE_BUILD_BUG_ON(sizeof(reta.bytes) != IGC_RSS_RDT_REG_SIZE);
>   		for (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) {
>   			if (mask & (1u << j))
>   				reta.bytes[j] =
> @@ -2318,6 +2322,8 @@ static int eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
>   		return -EINVAL;
>   	}
>   
> +	RTE_BUILD_BUG_ON(ETH_RSS_RETA_SIZE_128 % IGC_RSS_RDT_REG_SIZE);
> +
>   	/* read redirection table */
>   	for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE) {
>   		union igc_rss_reta_reg reta;
> @@ -2330,12 +2336,14 @@ static int eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
>   				IGC_RSS_RDT_REG_SIZE_MASK);
>   
>   		/* if no need to read register */
> -		if (!mask)
> +		if (!mask ||
> +			shift > (RTE_RETA_GROUP_SIZE - IGC_RSS_RDT_REG_SIZE))


the same as above.


>   			continue;
>   
>   		/* read register and get the queue index */
>   		reta.dword = IGC_READ_REG_LE_VALUE(hw,
>   				IGC_RETA(i / IGC_RSS_RDT_REG_SIZE));
> +		RTE_BUILD_BUG_ON(sizeof(reta.bytes) != IGC_RSS_RDT_REG_SIZE);


need null line or no need, please check it at the place and before.


>   		for (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) {
>   			if (mask & (1u << j))
>   				reta_conf[idx].reta[shift + j] = reta.bytes[j];
Alvin Zhang May 7, 2020, 8:08 a.m. UTC | #2 
Hi Jia,
First of all, this is a coverity issue, and it's really a false positives. But do some macro checking will improve code robustness.

Thanks,
Alvin

> -----Original Message-----
> From: Guo, Jia
> Sent: Thursday, May 7, 2020 2:30 PM
> To: Zhang, AlvinX <alvinx.zhang@intel.com>; dev@dpdk.org
> Cc: Zhao1, Wei <wei.zhao1@intel.com>; Ye, Xiaolong
> <xiaolong.ye@intel.com>
> Subject: Re: [PATCH] net/igc: fix memory illegal accesses
> 
> hi, alvin
> 
> 
> On 5/7/2020 10:01 AM, alvinx.zhang@intel.com wrote:
> > From: Alvin Zhang <alvinx.zhang@intel.com>
> >
> > Add memory access out-of-bounds check.
> 
> 
> Could you explain why add ...?  If not add, what issue?
> 
> 
> >
> > Fixes: bd3fcf0d0fa1 (net/igc: support RSS)
> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
> > ---
> >   drivers/net/igc/igc_ethdev.c | 12 ++++++++++--
> >   1 file changed, 10 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/net/igc/igc_ethdev.c
> > b/drivers/net/igc/igc_ethdev.c index 16d98c6..ced8ffd 100644
> > --- a/drivers/net/igc/igc_ethdev.c
> > +++ b/drivers/net/igc/igc_ethdev.c
> > @@ -2266,6 +2266,8 @@ static int eth_igc_vlan_tpid_set(struct
> rte_eth_dev *dev,
> >   		return -EINVAL;
> >   	}
> >
> > +	RTE_BUILD_BUG_ON(ETH_RSS_RETA_SIZE_128 %
> IGC_RSS_RDT_REG_SIZE);
> > +
> >   	/* set redirection table */
> >   	for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE)
> {
> >   		union igc_rss_reta_reg reta, reg;
> > @@ -2278,7 +2280,8 @@ static int eth_igc_vlan_tpid_set(struct
> rte_eth_dev *dev,
> >   				IGC_RSS_RDT_REG_SIZE_MASK);
> >
> >   		/* if no need to update the register */
> > -		if (!mask)
> > +		if (!mask ||
> > +			shift > (RTE_RETA_GROUP_SIZE -
> IGC_RSS_RDT_REG_SIZE))
> 
> 
> alignment should be match above parentheses.
> 
> 
> >   			continue;
> >
> >   		/* check mask whether need to read the register value first
> */ @@
> > -2289,6 +2292,7 @@ static int eth_igc_vlan_tpid_set(struct rte_eth_dev
> *dev,
> >   					IGC_RETA(i /
> IGC_RSS_RDT_REG_SIZE));
> >
> >   		/* update the register */
> > +		RTE_BUILD_BUG_ON(sizeof(reta.bytes) !=
> IGC_RSS_RDT_REG_SIZE);
> >   		for (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) {
> >   			if (mask & (1u << j))
> >   				reta.bytes[j] =
> > @@ -2318,6 +2322,8 @@ static int eth_igc_vlan_tpid_set(struct
> rte_eth_dev *dev,
> >   		return -EINVAL;
> >   	}
> >
> > +	RTE_BUILD_BUG_ON(ETH_RSS_RETA_SIZE_128 %
> IGC_RSS_RDT_REG_SIZE);
> > +
> >   	/* read redirection table */
> >   	for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE)
> {
> >   		union igc_rss_reta_reg reta;
> > @@ -2330,12 +2336,14 @@ static int eth_igc_vlan_tpid_set(struct
> rte_eth_dev *dev,
> >   				IGC_RSS_RDT_REG_SIZE_MASK);
> >
> >   		/* if no need to read register */
> > -		if (!mask)
> > +		if (!mask ||
> > +			shift > (RTE_RETA_GROUP_SIZE -
> IGC_RSS_RDT_REG_SIZE))
> 
> 
> the same as above.
> 
> 
> >   			continue;
> >
> >   		/* read register and get the queue index */
> >   		reta.dword = IGC_READ_REG_LE_VALUE(hw,
> >   				IGC_RETA(i / IGC_RSS_RDT_REG_SIZE));
> > +		RTE_BUILD_BUG_ON(sizeof(reta.bytes) !=
> IGC_RSS_RDT_REG_SIZE);
> 
> 
> need null line or no need, please check it at the place and before.
> 
> 
> >   		for (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) {
> >   			if (mask & (1u << j))
> >   				reta_conf[idx].reta[shift + j] = reta.bytes[j];
diff mbox series

Patch

diff --git a/drivers/net/igc/igc_ethdev.c b/drivers/net/igc/igc_ethdev.c
index 16d98c6..ced8ffd 100644
--- a/drivers/net/igc/igc_ethdev.c
+++ b/drivers/net/igc/igc_ethdev.c
@@ -2266,6 +2266,8 @@  static int eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
 		return -EINVAL;
 	}
 
+	RTE_BUILD_BUG_ON(ETH_RSS_RETA_SIZE_128 % IGC_RSS_RDT_REG_SIZE);
+
 	/* set redirection table */
 	for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE) {
 		union igc_rss_reta_reg reta, reg;
@@ -2278,7 +2280,8 @@  static int eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
 				IGC_RSS_RDT_REG_SIZE_MASK);
 
 		/* if no need to update the register */
-		if (!mask)
+		if (!mask ||
+			shift > (RTE_RETA_GROUP_SIZE - IGC_RSS_RDT_REG_SIZE))
 			continue;
 
 		/* check mask whether need to read the register value first */
@@ -2289,6 +2292,7 @@  static int eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
 					IGC_RETA(i / IGC_RSS_RDT_REG_SIZE));
 
 		/* update the register */
+		RTE_BUILD_BUG_ON(sizeof(reta.bytes) != IGC_RSS_RDT_REG_SIZE);
 		for (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) {
 			if (mask & (1u << j))
 				reta.bytes[j] =
@@ -2318,6 +2322,8 @@  static int eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
 		return -EINVAL;
 	}
 
+	RTE_BUILD_BUG_ON(ETH_RSS_RETA_SIZE_128 % IGC_RSS_RDT_REG_SIZE);
+
 	/* read redirection table */
 	for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE) {
 		union igc_rss_reta_reg reta;
@@ -2330,12 +2336,14 @@  static int eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
 				IGC_RSS_RDT_REG_SIZE_MASK);
 
 		/* if no need to read register */
-		if (!mask)
+		if (!mask ||
+			shift > (RTE_RETA_GROUP_SIZE - IGC_RSS_RDT_REG_SIZE))
 			continue;
 
 		/* read register and get the queue index */
 		reta.dword = IGC_READ_REG_LE_VALUE(hw,
 				IGC_RETA(i / IGC_RSS_RDT_REG_SIZE));
+		RTE_BUILD_BUG_ON(sizeof(reta.bytes) != IGC_RSS_RDT_REG_SIZE);
 		for (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) {
 			if (mask & (1u << j))
 				reta_conf[idx].reta[shift + j] = reta.bytes[j];