[1/2] config/arm: add SVE control flag

Message ID 20220505142744.1423344-1-rbhansali@marvell.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series [1/2] config/arm: add SVE control flag |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Rahul Bhansali May 5, 2022, 2:27 p.m. UTC
  This add the control flag for SVE to enable or disable
RTE_HAS_SVE_ACLE macro in the build.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
---
 config/arm/meson.build | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
  

Comments

Bruce Richardson May 5, 2022, 2:39 p.m. UTC | #1
On Thu, May 05, 2022 at 07:57:43PM +0530, Rahul Bhansali wrote:
> This add the control flag for SVE to enable or disable
> RTE_HAS_SVE_ACLE macro in the build.
> 
> Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
> ---
>  config/arm/meson.build | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 8aead74086..dafb342cc6 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -603,7 +603,8 @@ if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
>      compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
>  endif
>  
> -if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
> +if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and
> +    soc_config.get('sve', true))

Please double-indent this so that it does not line up with the following
lines of the block.

>      compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
>      if (cc.check_header('arm_sve.h'))
>          dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
> -- 
> 2.25.1
>
  
fengchengwen May 6, 2022, 2:23 a.m. UTC | #2
On 2022/5/5 22:27, Rahul Bhansali wrote:
> This add the control flag for SVE to enable or disable
> RTE_HAS_SVE_ACLE macro in the build.
> 
> Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
> ---
>  config/arm/meson.build | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 8aead74086..dafb342cc6 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -603,7 +603,8 @@ if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
>      compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
>  endif
>  
> -if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
> +if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and
> +    soc_config.get('sve', true))

The march_features already contain the flag.
If the cpu support 'sve' then it could declare it in march_features, please refer Kunpeng 930:

        '0xd02': {
            'march': 'armv8.2-a',
            'march_features': ['crypto', 'sve'],
            'flags': [
                ['RTE_MACHINE', '"Kunpeng 930"'],
                ['RTE_ARM_FEATURE_ATOMICS', true],
                ['RTE_MAX_LCORE', 1280],
                ['RTE_MAX_NUMA_NODES', 16]
            ]
        }

>      compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
>      if (cc.check_header('arm_sve.h'))
>          dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
>
  
Rahul Bhansali May 6, 2022, 2:16 p.m. UTC | #3
> -----Original Message-----
> From: Bruce Richardson <bruce.richardson@intel.com>
> Sent: Thursday, May 5, 2022 8:09 PM
> To: Rahul Bhansali <rbhansali@marvell.com>
> Cc: dev@dpdk.org; Ruifeng Wang <ruifeng.wang@arm.com>; Jan Viktorin
> <viktorin@rehivetech.com>; Jerin Jacob Kollanukkaran <jerinj@marvell.com>
> Subject: [EXT] Re: [PATCH 1/2] config/arm: add SVE control flag
> 
> External Email
> 
> ----------------------------------------------------------------------
> On Thu, May 05, 2022 at 07:57:43PM +0530, Rahul Bhansali wrote:
> > This add the control flag for SVE to enable or disable
> > RTE_HAS_SVE_ACLE macro in the build.
> >
> > Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
> > ---
> >  config/arm/meson.build | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > 8aead74086..dafb342cc6 100644
> > --- a/config/arm/meson.build
> > +++ b/config/arm/meson.build
> > @@ -603,7 +603,8 @@ if (cc.get_define('__ARM_NEON', args: machine_args)
> != '' or
> >      compile_time_cpuflags += ['RTE_CPUFLAG_NEON']  endif
> >
> > -if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
> > +if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and
> > +    soc_config.get('sve', true))
> 
> Please double-indent this so that it does not line up with the following lines of
> the block.
> 

Ack, will send v2 with this double-indent change.

> >      compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
> >      if (cc.check_header('arm_sve.h'))
> >          dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)
> > --
> > 2.25.1
> >
  

Patch

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 8aead74086..dafb342cc6 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -603,7 +603,8 @@  if (cc.get_define('__ARM_NEON', args: machine_args) != '' or
     compile_time_cpuflags += ['RTE_CPUFLAG_NEON']
 endif
 
-if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != ''
+if (cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' and
+    soc_config.get('sve', true))
     compile_time_cpuflags += ['RTE_CPUFLAG_SVE']
     if (cc.check_header('arm_sve.h'))
         dpdk_conf.set('RTE_HAS_SVE_ACLE', 1)