[v3,13/13] net/cnxk: handle hard expiry events
Checks
Commit Message
From: Vamsi Attunuru <vattunuru@marvell.com>
Based on the hard limits configured in the SA context,
PMD passes corresponding event subtype to the application
to notify hard expiry event
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
---
drivers/net/cnxk/cn10k_ethdev_sec.c | 6 ++++++
1 file changed, 6 insertions(+)
Comments
On Fri, Oct 14, 2022 at 11:14 AM Nithin Dabilpuram
<ndabilpuram@marvell.com> wrote:
>
> From: Vamsi Attunuru <vattunuru@marvell.com>
>
> Based on the hard limits configured in the SA context,
> PMD passes corresponding event subtype to the application
> to notify hard expiry event
>
> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Updated the git commit as follows and applied to
dpdk-next-net-mrvl/for-next-net. Thanks
commit b05f3b8dd70254ff40f02a9783d6a3c419f3fa2c
Author: Vamsi Attunuru <vattunuru@marvell.com>
Date: Fri Oct 14 11:13:17 2022 +0530
net/cnxk: handle hard expiry events
Based on the hard limits configured in the SA context,
PMD passes corresponding event subtype to the application
to notify hard expiry event
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
commit 39d00803ac14c5c82f066bac26becd22d98c8a25
Author: Nithin Dabilpuram <ndabilpuram@marvell.com>
Date: Fri Oct 14 11:13:16 2022 +0530
net/cnxk: remove duplicate mempool debug checks
Remove duplicate mempool debug checks for mbufs received.
Fixes: 592642c494b1 ("net/cnxk: align prefetches to CN10K cache model")
Cc: stable@dpdk.org
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
commit 800400d9125b093990155bc0b127ad2ec3df1018
Author: Nithin Dabilpuram <ndabilpuram@marvell.com>
Date: Fri Oct 14 11:13:15 2022 +0530
net/cnxk: remove unnecessary DPTR update
Removed unnecessary datapointer(DPTR) update and remove ESN update
from microcode command word 0 based on the latest microcode.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
commit d5718d9c467090505864f843a2838511ea48167d
Author: Sunil Kumar Kori <skori@marvell.com>
Date: Fri Oct 14 11:13:14 2022 +0530
common/cnxk: fix channel to BPID mapping
As per recent change in Linux-5.4.x AF driver, mailbox is updated to
configure mapping between channel and BPID.
Due to mbox mismatch, PFC was broken. Patch syncs mailbox definition
for the same. Also fixes the PFC configuration issues.
Fixes: ff1400aa9d34 ("net/cnxk: add receive channel backpressure for SDP")
Cc: stable@dpdk.org
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
commit 3adb75fe4d5018ee556850af49aaebb19a99ba5c
Author: Vamsi Attunuru <vattunuru@marvell.com>
Date: Fri Oct 14 11:13:13 2022 +0530
net/cnxk: handle SA soft packet and byte expiry events
Handle SA soft packet and byte expiry event for Inline outbound SA.
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
commit 0ec8b45ea8742f468e10e04603a426a27d1c5a41
Author: Satha Rao <skoteshwar@marvell.com>
Date: Fri Oct 14 11:13:12 2022 +0530
common/cnxk: set hysteresis bit to one
Setting non zero FC_HYST_BITS to reduce mesh traffic to
reduce system resources.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
commit 78f832e5ef5b694ac0b4148ec1ed1e69e73932a2
Author: Satha Rao <skoteshwar@marvell.com>
Date: Fri Oct 14 11:13:11 2022 +0530
common/cnxk: sync NIX HW info mbox structure with kernel
Sync nix_hw_info structure with kernel.
Maintain default RR_QUANTUM for VF TL2 same as kernel to make
equal distribution among all VFs.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
commit a5fc439a0bcc66c1f501a70f5439bbfe413d02b7
Author: Satha Rao <skoteshwar@marvell.com>
Date: Fri Oct 14 11:13:10 2022 +0530
common/cnxk: fix schedule weight update
Each TX schedule config mail box supports a maximum 20 register updates.
This patch will send node weight updates in multiple mailboxes when
TM is created with more than 20 scheduler nodes.
Fixes: 464c9f919321 ("common/cnxk: support NIX TM dynamic update")
Cc: stable@dpdk.org
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
commit 0aa3a8bf816d76a8a219cdc2c7733072b92ecbec
Author: Nithin Dabilpuram <ndabilpuram@marvell.com>
Date: Fri Oct 14 11:13:09 2022 +0530
common/cnxk: fix RQ mask config for cn10kb chip
RQ mask config needs to enable SPB_ENA in order for zero for
being able to override it with meta AURA.
Also fix flow control config to catch invalid rxchan config
errors.
Fixes: ddf955d3917e ("common/cnxk: support CPT second pass")
Fixes: da57d4589a6f ("common/cnxk: support NIX flow control")
Cc: stable@dpdk.org
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
commit 87d6f8ce329212bb33a7e26b6f021cc11b900865
Author: Nithin Dabilpuram <ndabilpuram@marvell.com>
Date: Fri Oct 14 11:13:08 2022 +0530
net/cnxk: use NIX Tx offset for cn10kb
In outbound inline case, use NIX Tx offset instead of
NIX Tx address for cn10kb as per new instruction format.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
commit 48b95a4b46207172645d8892265e79accfd2c6a3
Author: Nithin Dabilpuram <ndabilpuram@marvell.com>
Date: Fri Oct 14 11:13:07 2022 +0530
net/cnxk: fix later skip to include mbuf priv
Fix later skip to include mbuf priv data as mbuf->buf_addr
is populated based on calculation including per-mbuf priv area.
Fixes: 706eeae60757 ("net/cnxk: add multi-segment Rx for CN10K")
cc: stable@dpdk.org
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
commit 2d394491f7a3492b87f590c4e789c17d41d89230
Author: Nithin Dabilpuram <ndabilpuram@marvell.com>
Date: Fri Oct 14 11:13:06 2022 +0530
common/cnxk: add devargs for soft expiry poll frequency
Add support to override soft expiry poll frequency via devargs.
Also provide helper API to indicate reassembly support on a chip
and documentation for devargs that are already present.
Fixes: 780b9c89241b ("net/cnxk: support zero AURA for inline meta")
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
commit 8614ba649706fadefa55a111c1d1bb4882ca0c91
Author: Sathesh Edara <sedara@marvell.com>
Date: Fri Oct 14 11:13:05 2022 +0530
common/cnxk: set MTU size on SDP based on SoC type
Set maximum frame size on SDP NIX side to 16KB for CN93 A0 and B0,
CNF95N A0 and CNF95O A0 SOC type. Rest of the SoCs SDP NIX to 64KB.
Signed-off-by: Sathesh Edara <sedara@marvell.com>
> ---
> drivers/net/cnxk/cn10k_ethdev_sec.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/net/cnxk/cn10k_ethdev_sec.c b/drivers/net/cnxk/cn10k_ethdev_sec.c
> index ce1b10d885..ed5c335787 100644
> --- a/drivers/net/cnxk/cn10k_ethdev_sec.c
> +++ b/drivers/net/cnxk/cn10k_ethdev_sec.c
> @@ -479,6 +479,12 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args, uint32_t soft_exp_event)
> case ROC_IE_OT_UCC_ERR_SA_OVERFLOW:
> desc.subtype = RTE_ETH_EVENT_IPSEC_ESN_OVERFLOW;
> break;
> + case ROC_IE_OT_UCC_ERR_SA_EXPIRED:
> + if (sa->w2.s.life_unit == ROC_IE_OT_SA_LIFE_UNIT_PKTS)
> + desc.subtype = RTE_ETH_EVENT_IPSEC_SA_PKT_HARD_EXPIRY;
> + else
> + desc.subtype = RTE_ETH_EVENT_IPSEC_SA_BYTE_HARD_EXPIRY;
> + break;
> case ROC_IE_OT_UCC_ERR_PKT_IP:
> warn_cnt++;
> if (warn_cnt % 10000 == 0)
> --
> 2.25.1
>
@@ -479,6 +479,12 @@ cn10k_eth_sec_sso_work_cb(uint64_t *gw, void *args, uint32_t soft_exp_event)
case ROC_IE_OT_UCC_ERR_SA_OVERFLOW:
desc.subtype = RTE_ETH_EVENT_IPSEC_ESN_OVERFLOW;
break;
+ case ROC_IE_OT_UCC_ERR_SA_EXPIRED:
+ if (sa->w2.s.life_unit == ROC_IE_OT_SA_LIFE_UNIT_PKTS)
+ desc.subtype = RTE_ETH_EVENT_IPSEC_SA_PKT_HARD_EXPIRY;
+ else
+ desc.subtype = RTE_ETH_EVENT_IPSEC_SA_BYTE_HARD_EXPIRY;
+ break;
case ROC_IE_OT_UCC_ERR_PKT_IP:
warn_cnt++;
if (warn_cnt % 10000 == 0)