diff mbox series

[12/15] common/cnxk: enable one to one SQ QINT mapping

Message ID 20230303081013.589868-12-ndabilpuram@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: Jerin Jacob
Headers
Series [01/15] net/cnxk: resolve sefgault caused during transmit completion |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Nithin Dabilpuram March 3, 2023, 8:10 a.m. UTC 
  From: Harman Kalra <hkalra@marvell.com>

Enabling one to one mapping between SQ to 64 QINTs per LF. So in case of
SQ interrupt event NIX can deliver associated QINT MSI-X interrupt to
software and increment respective QINT count CSR.

While for some cn10k chip models keeping the workaround (i.e. all SQs
assigned to same QINT index), for errata where NIX may use an incorrect
QINT_IDX for SQ interrupts.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
---
 drivers/common/cnxk/roc_errata.h    |  8 ++++++++
 drivers/common/cnxk/roc_nix_queue.c | 21 +++++++++++----------
 2 files changed, 19 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_errata.h b/drivers/common/cnxk/roc_errata.h
index 36e6db467a..356f9ca626 100644
--- a/drivers/common/cnxk/roc_errata.h
+++ b/drivers/common/cnxk/roc_errata.h
@@ -98,4 +98,12 @@  roc_errata_nix_sdp_send_has_mtu_size_16k(void)
 		roc_model_is_cn96_a0() || roc_model_is_cn96_b0());
 }
 
+/* Errata IPBUNIXTX-39300 */
+static inline bool
+roc_errata_nix_assign_incorrect_qint(void)
+{
+	return (roc_model_is_cn10ka_a0() || roc_model_is_cnf10ka_a0() ||
+		roc_model_is_cnf10kb_a0() || roc_model_is_cn10ka_a1());
+}
+
 #endif /* _ROC_ERRATA_H_ */
diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c
index 464ee0b984..21bfe7d498 100644
--- a/drivers/common/cnxk/roc_nix_queue.c
+++ b/drivers/common/cnxk/roc_nix_queue.c
@@ -1103,11 +1103,8 @@  sq_cn9k_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum,
 	aq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
 
 	/* Many to one reduction */
-	/* Assigning QINT 0 to all the SQs, an errata exists where NIXTX can
-	 * send incorrect QINT_IDX when reporting queue interrupt (QINT). This
-	 * might result in software missing the interrupt.
-	 */
-	aq->sq.qint_idx = 0;
+	aq->sq.qint_idx = sq->qid % nix->qints;
+
 	return 0;
 }
 
@@ -1237,11 +1234,15 @@  sq_init(struct nix *nix, struct roc_nix_sq *sq, uint32_t rr_quantum, uint16_t sm
 	aq->sq.sq_int_ena |= BIT(NIX_SQINT_SEND_ERR);
 	aq->sq.sq_int_ena |= BIT(NIX_SQINT_MNQ_ERR);
 
-	/* Assigning QINT 0 to all the SQs, an errata exists where NIXTX can
-	 * send incorrect QINT_IDX when reporting queue interrupt (QINT). This
-	 * might result in software missing the interrupt.
-	 */
-	aq->sq.qint_idx = 0;
+	/* Many to one reduction */
+	aq->sq.qint_idx = sq->qid % nix->qints;
+	if (roc_errata_nix_assign_incorrect_qint()) {
+		/* Assigning QINT 0 to all the SQs, an errata exists where NIXTX can
+		 * send incorrect QINT_IDX when reporting queue interrupt (QINT). This
+		 * might result in software missing the interrupt.
+		 */
+		aq->sq.qint_idx = 0;
+	}
 	return 0;
 }