@@ -10,7 +10,6 @@
#include <sys/stat.h>
#include <sys/mman.h>
#include <sys/sysmacros.h>
-#include <linux/pci_regs.h>
#if defined(RTE_ARCH_X86)
#include <sys/io.h>
@@ -77,35 +76,6 @@ pci_uio_mmio_write(const struct rte_pci_device *dev, int bar,
return len;
}
-static int
-pci_uio_set_bus_master(int dev_fd)
-{
- uint16_t reg;
- int ret;
-
- ret = pread(dev_fd, ®, sizeof(reg), PCI_COMMAND);
- if (ret != sizeof(reg)) {
- RTE_LOG(ERR, EAL,
- "Cannot read command from PCI config space!\n");
- return -1;
- }
-
- /* return if bus mastering is already on */
- if (reg & PCI_COMMAND_MASTER)
- return 0;
-
- reg |= PCI_COMMAND_MASTER;
-
- ret = pwrite(dev_fd, ®, sizeof(reg), PCI_COMMAND);
- if (ret != sizeof(reg)) {
- RTE_LOG(ERR, EAL,
- "Cannot write command to PCI config space!\n");
- return -1;
- }
-
- return 0;
-}
-
static int
pci_mknod_uio_dev(const char *sysfs_uio_path, unsigned uio_num)
{
@@ -299,7 +269,7 @@ pci_uio_alloc_resource(struct rte_pci_device *dev,
goto error;
/* set bus master that is not done by uio_pci_generic */
- if (pci_uio_set_bus_master(uio_cfg_fd)) {
+ if (rte_pci_set_bus_master(dev, true)) {
RTE_LOG(ERR, EAL, "Cannot set up bus mastering!\n");
goto error;
}
@@ -223,42 +223,6 @@ pci_vfio_enable_bus_memory(struct rte_pci_device *dev, int dev_fd)
return 0;
}
-/* set PCI bus mastering */
-static int
-pci_vfio_set_bus_master(const struct rte_pci_device *dev, int dev_fd, bool op)
-{
- uint64_t size, offset;
- uint16_t reg;
- int ret;
-
- if (pci_vfio_get_region(dev, VFIO_PCI_CONFIG_REGION_INDEX,
- &size, &offset) != 0) {
- RTE_LOG(ERR, EAL, "Cannot get offset of CONFIG region.\n");
- return -1;
- }
-
- ret = pread64(dev_fd, ®, sizeof(reg), offset + PCI_COMMAND);
- if (ret != sizeof(reg)) {
- RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n");
- return -1;
- }
-
- if (op)
- /* set the master bit */
- reg |= PCI_COMMAND_MASTER;
- else
- reg &= ~(PCI_COMMAND_MASTER);
-
- ret = pwrite64(dev_fd, ®, sizeof(reg), offset + PCI_COMMAND);
-
- if (ret != sizeof(reg)) {
- RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n");
- return -1;
- }
-
- return 0;
-}
-
/* set up interrupt support (but not enable interrupts) */
static int
pci_vfio_setup_interrupts(struct rte_pci_device *dev, int vfio_dev_fd)
@@ -535,8 +499,7 @@ pci_rte_vfio_setup_device(struct rte_pci_device *dev, int vfio_dev_fd)
return -1;
}
- /* set bus mastering for the device */
- if (pci_vfio_set_bus_master(dev, vfio_dev_fd, true)) {
+ if (rte_pci_set_bus_master(dev, true)) {
RTE_LOG(ERR, EAL, "Cannot set up bus mastering!\n");
return -1;
}
@@ -1226,7 +1189,7 @@ pci_vfio_unmap_resource_primary(struct rte_pci_device *dev)
if (vfio_dev_fd < 0)
return -1;
- if (pci_vfio_set_bus_master(dev, vfio_dev_fd, false)) {
+ if (rte_pci_set_bus_master(dev, false)) {
RTE_LOG(ERR, EAL, "%s cannot unset bus mastering for PCI device!\n",
pci_addr);
return -1;
@@ -49,29 +49,6 @@ static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
static int hns3vf_dev_link_update(struct rte_eth_dev *eth_dev,
__rte_unused int wait_to_complete);
-/* set PCI bus mastering */
-static int
-hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
-{
- uint16_t reg;
- int ret;
-
- ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND);
- if (ret < 0) {
- PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
- PCI_COMMAND);
- return ret;
- }
-
- if (op)
- /* set the master bit */
- reg |= PCI_COMMAND_MASTER;
- else
- reg &= ~(PCI_COMMAND_MASTER);
-
- return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND);
-}
-
/**
* hns3vf_find_pci_capability - lookup a capability in the PCI capability list
* @cap: the capability
@@ -2140,7 +2117,7 @@ hns3vf_reinit_dev(struct hns3_adapter *hns)
if (hw->reset.level == HNS3_VF_FULL_RESET) {
rte_intr_disable(pci_dev->intr_handle);
- ret = hns3vf_set_bus_master(pci_dev, true);
+ ret = rte_pci_set_bus_master(pci_dev, true);
if (ret < 0) {
hns3_err(hw, "failed to set pci bus, ret = %d", ret);
return ret;
@@ -1061,26 +1061,10 @@ s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable)
{
struct rte_pci_device *pci_dev = (struct rte_pci_device *)hw->back;
s32 status = 0;
- s32 ret = 0;
u32 i;
- u16 reg;
- ret = rte_pci_read_config(pci_dev, ®,
- sizeof(reg), PCI_COMMAND);
- if (ret != sizeof(reg)) {
- DEBUGOUT("Cannot read command from PCI config space!\n");
- return -1;
- }
-
- if (enable)
- reg |= PCI_COMMAND_MASTER;
- else
- reg &= ~PCI_COMMAND_MASTER;
-
- ret = rte_pci_write_config(pci_dev, ®,
- sizeof(reg), PCI_COMMAND);
- if (ret != sizeof(reg)) {
- DEBUGOUT("Cannot write command to PCI config space!\n");
+ if (rte_pci_set_bus_master(pci_dev, enable) < 0) {
+ DEBUGOUT("Cannot configure PCI bus master\n");
return -1;
}
@@ -181,7 +181,4 @@ static inline u64 REVERT_BIT_MASK64(u64 mask)
#define ETH_P_8021Q 0x8100
#define ETH_P_8021AD 0x88A8
-#define PCI_COMMAND 0x04
-#define PCI_COMMAND_MASTER 0x4
-
#endif /* _NGBE_OS_H_ */