diff mbox series

[11/31] common/cnxk: fix different size bit operations

Message ID 20230811085805.441256-11-ndabilpuram@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: Jerin Jacob
Headers
Series [01/31] common/cnxk: add aura ref count mechanism |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Nithin Dabilpuram Aug. 11, 2023, 8:57 a.m. UTC 
  From: Akhil Goyal <gakhil@marvell.com>

Bitwise or is being done on relchan which is 32 bit,
but the result is 64 bit, hence typecast to uint64_t.

Fixes: 8f867a87b9c5 ("common/cnxk: enable SDP channel backpressure to TL4")
Fixes: 0885429c3028 ("common/cnxk: add NIX TM hierarchy enable/disable")

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
---
 drivers/common/cnxk/roc_nix_tm_utils.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/common/cnxk/roc_nix_tm_utils.c b/drivers/common/cnxk/roc_nix_tm_utils.c
index 3840d6d457..ce26ddff50 100644
--- a/drivers/common/cnxk/roc_nix_tm_utils.c
+++ b/drivers/common/cnxk/roc_nix_tm_utils.c
@@ -588,7 +588,7 @@  nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,
 			reg[k] = NIX_AF_TL4X_SDP_LINK_CFG(schq);
 			regval[k] = BIT_ULL(12);
 			regval[k] |= BIT_ULL(13);
-			regval[k] |= relchan;
+			regval[k] |= (uint64_t)relchan;
 			k++;
 		}
 		break;
@@ -606,7 +606,7 @@  nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,
 		if (!nix->sdp_link &&
 		    nix->tm_link_cfg_lvl == NIX_TXSCH_LVL_TL3) {
 			reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
-			regval[k] = BIT_ULL(12) | relchan;
+			regval[k] = BIT_ULL(12) | (uint64_t)relchan;
 			k++;
 		}
 
@@ -625,7 +625,7 @@  nix_tm_topology_reg_prep(struct nix *nix, struct nix_tm_node *node,
 		if (!nix->sdp_link &&
 		    nix->tm_link_cfg_lvl == NIX_TXSCH_LVL_TL2) {
 			reg[k] = NIX_AF_TL3_TL2X_LINKX_CFG(schq, link);
-			regval[k] = BIT_ULL(12) | relchan;
+			regval[k] = BIT_ULL(12) | (uint64_t)relchan;
 			k++;
 		}