diff mbox series

[v3,11/15] pci: define some extended capability constants

Message ID 20230914123615.1705654-12-david.marchand@redhat.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers
Series Cleanup PCI(e) drivers |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

David Marchand Sept. 14, 2023, 12:36 p.m. UTC 
  Define some PCI extended capability constants and use them in existing
drivers.

Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: Chenbo Xia <chenbo.xia@intel.com>
Signed-off-by: David Marchand <david.marchand@redhat.com>
---
Changes since v2:
- fixed existing SRIOV comment,

---
 drivers/event/dlb2/pf/dlb2_main.c | 7 ++-----
 lib/pci/rte_pci.h                 | 6 ++++--
 2 files changed, 6 insertions(+), 7 deletions(-)

Comments

Sevincer, Abdullah Sept. 15, 2023, 4:27 p.m. UTC | #1 
Acked-by: Abdullah Sevincer <abdullah.sevincer@intel.com>
diff mbox series

Patch

diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c
index 8d960edef6..29e3001627 100644
--- a/drivers/event/dlb2/pf/dlb2_main.c
+++ b/drivers/event/dlb2/pf/dlb2_main.c
@@ -27,9 +27,6 @@ 
 #define NO_OWNER_VF 0	/* PF ONLY! */
 #define NOT_VF_REQ false /* PF ONLY! */
 
-#define DLB2_PCI_EXT_CAP_ID_PRI   0x13
-#define DLB2_PCI_EXT_CAP_ID_ACS   0xD
-
 #define DLB2_PCI_PRI_CTRL_ENABLE         0x1
 #define DLB2_PCI_PRI_ALLOC_REQ           0xC
 #define DLB2_PCI_PRI_CTRL                0x4
@@ -263,7 +260,7 @@  dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
 	if (rte_pci_read_config(pdev, &slt_word2, 2, off) != 2)
 		slt_word2 = 0;
 
-	off = DLB2_PCI_EXT_CAP_ID_PRI;
+	off = RTE_PCI_EXT_CAP_ID_PRI;
 	pri_cap_offset = rte_pci_find_ext_capability(pdev, off);
 
 	if (pri_cap_offset >= 0) {
@@ -490,7 +487,7 @@  dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
 		}
 	}
 
-	off = DLB2_PCI_EXT_CAP_ID_ACS;
+	off = RTE_PCI_EXT_CAP_ID_ACS;
 	acs_cap_offset = rte_pci_find_ext_capability(pdev, off);
 
 	if (acs_cap_offset >= 0) {
diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
index 00ce390c1c..1fdca91f8b 100644
--- a/lib/pci/rte_pci.h
+++ b/lib/pci/rte_pci.h
@@ -98,9 +98,11 @@  extern "C" {
 
 #define RTE_PCI_EXT_CAP_ID_ERR		0x01	/* Advanced Error Reporting */
 #define RTE_PCI_EXT_CAP_ID_DSN		0x03	/* Device Serial Number */
-#define RTE_PCI_EXT_CAP_ID_SRIOV	0x10	/* SR-IOV*/
+#define RTE_PCI_EXT_CAP_ID_ACS		0x0d	/* Access Control Services */
+#define RTE_PCI_EXT_CAP_ID_SRIOV	0x10	/* SR-IOV */
+#define RTE_PCI_EXT_CAP_ID_PRI		0x13	/* Page Request Interface */
 
-/* Single Root I/O Virtualization */
+/* Single Root I/O Virtualization (RTE_PCI_EXT_CAP_ID_SRIOV) */
 #define RTE_PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */
 #define RTE_PCI_SRIOV_CTRL		0x08	/* SR-IOV Control */
 #define RTE_PCI_SRIOV_INITIAL_VF	0x0c	/* Initial VFs */