diff mbox series

[v3,6/7] net/mlx5/hws: remove csum check from L3 ok check

Message ID 20231024175132.1435553-7-akozyrev@nvidia.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series ptype matching support in mlx5 |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Alexander Kozyrev Oct. 24, 2023, 5:51 p.m. UTC 
  From: Michael Baum <michaelba@nvidia.com>

This patch changes the integrity item behavior for HW steering.

Old behavior: the "ipv4_csum_ok" checks only IPv4 checksum and "l3_ok"
checks everything is ok including IPv4 checksum.

New behavior: the "l3_ok" checks everything is ok excluding IPv4
checksum.

This change enables matching "l3_ok" in IPv6 packets since for IPv6
packets "ipv4_csum_ok" is always miss.
For SW steering the old behavior is kept as same as for L4 ok.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
---
 doc/guides/nics/mlx5.rst              | 11 ++++++++---
 drivers/net/mlx5/hws/mlx5dr_definer.c |  6 ++----
 2 files changed, 10 insertions(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index c9e74948cc..8d7e0aad7e 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -663,12 +663,13 @@  Limitations
 
 - Integrity:
 
-  - Integrity offload is enabled starting from **ConnectX-6 Dx**.
   - Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``.
   - ``level`` value 0 references outer headers.
   - Negative integrity item verification is not supported.
-  - Multiple integrity items not supported in a single flow rule.
-  - Flow rule items supplied by application must explicitly specify network headers referred by integrity item.
+  - With SW steering (``dv_flow_en=1``)
+    - Integrity offload is enabled starting from **ConnectX-6 Dx**.
+    - Multiple integrity items not supported in a single flow rule.
+    - Flow rule items supplied by application must explicitly specify network headers referred by integrity item.
     For example, if integrity item mask sets ``l4_ok`` or ``l4_csum_ok`` bits, reference to L4 network header,
     TCP or UDP, must be in the rule pattern as well::
 
@@ -676,6 +677,10 @@  Limitations
 
       flow create 0 ingress pattern integrity level is 0 value mask l4_ok value spec l4_ok / eth / ipv4 proto is udp / end …
 
+  - With HW steering (``dv_flow_en=2``)
+    - The ``l3_ok`` field represents all L3 checks, but nothing about whether IPv4 checksum ok.
+    - The ``l4_ok`` field represents all L4 checks including L4 checksum ok.
+
 - Connection tracking:
 
   - Cannot co-exist with ASO meter, ASO age action in a single flow rule.
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 0e1035c6bd..c752896ca7 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -380,10 +380,8 @@  mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc,
 	uint32_t ok1_bits = 0;
 
 	if (v->l3_ok)
-		ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) |
-				    BIT(MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK) :
-				    BIT(MLX5DR_DEFINER_OKS1_FIRST_L3_OK) |
-				    BIT(MLX5DR_DEFINER_OKS1_FIRST_IPV4_CSUM_OK);
+		ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) :
+				    BIT(MLX5DR_DEFINER_OKS1_FIRST_L3_OK);
 
 	if (v->ipv4_csum_ok)
 		ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_IPV4_CSUM_OK) :