diff mbox series

[v2] eal/x86: add AMD vendor check to choose TSC calibration

Message ID 20231123072730.22948-1-sivaprasad.tummala@amd.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers
Series [v2] eal/x86: add AMD vendor check to choose TSC calibration |

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ci/checkpatch success coding style OK
ci/loongarch-compilation success Compilation OK
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ci/iol-intel-Performance success Performance Testing PASS
ci/iol-compile-amd64-testing success Testing PASS
ci/iol-sample-apps-testing success Testing PASS
ci/iol-unit-arm64-testing success Testing PASS
ci/iol-unit-amd64-testing success Testing PASS
ci/iol-compile-arm64-testing success Testing PASS

Commit Message

Sivaprasad Tummala Nov. 23, 2023, 7:27 a.m. UTC 
  AMD Epyc processors doesn't support get_tsc_freq_arch().
The patch allows graceful return to allow fallback to
alternate TSC calibration.

Fixes: 3dbc565e81a0 ("timer: honor arch-specific TSC frequency query")
Cc: jerin.jacob@caviumnetworks.com
Cc: stable@dpdk.org

Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
---
 lib/eal/x86/rte_cycles.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Comments

Ferruh Yigit Nov. 23, 2023, 10:29 a.m. UTC | #1 
On 11/23/2023 7:27 AM, Sivaprasad Tummala wrote:
> AMD Epyc processors doesn't support get_tsc_freq_arch().
> The patch allows graceful return to allow fallback to
> alternate TSC calibration.
> 
> Fixes: 3dbc565e81a0 ("timer: honor arch-specific TSC frequency query")
> Cc: jerin.jacob@caviumnetworks.com
> Cc: stable@dpdk.org
> 
> Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
> 

Acked-by: Ferruh Yigit <ferruh.yigit@amd.com>
Thomas Monjalon Feb. 13, 2024, 3:14 p.m. UTC | #2 
23/11/2023 11:29, Ferruh Yigit:
> On 11/23/2023 7:27 AM, Sivaprasad Tummala wrote:
> > AMD Epyc processors doesn't support get_tsc_freq_arch().
> > The patch allows graceful return to allow fallback to
> > alternate TSC calibration.
> > 
> > Fixes: 3dbc565e81a0 ("timer: honor arch-specific TSC frequency query")
> > Cc: jerin.jacob@caviumnetworks.com
> > Cc: stable@dpdk.org
> > 
> > Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
> 
> Acked-by: Ferruh Yigit <ferruh.yigit@amd.com>

Applied

I don't want to block longer this fix,
but I am not satisfied with the implementation.
David, Ferruh, Bruce and Morten were proposing some abstractions
for CPU features identification.
I think we should start a new enum in rte_cpuflags.h defining some
common CPU features, example is timer calibration here.

The function get_tsc_freq_arch() was already doing some __cpuid calls,
so it's one more, but please could you work on abstracting it in EAL?

Thank you
diff mbox series

Patch

diff --git a/lib/eal/x86/rte_cycles.c b/lib/eal/x86/rte_cycles.c
index 69ed59b4f0..f147a5231d 100644
--- a/lib/eal/x86/rte_cycles.c
+++ b/lib/eal/x86/rte_cycles.c
@@ -10,6 +10,10 @@ 
 #include <cpuid.h>
 #endif
 
+#define x86_vendor_amd(t1, t2, t3)        \
+	((t1 == 0x68747541) && /* htuA */   \
+	 (t2 == 0x444d4163) && /* DMAc */   \
+	 (t3 == 0x69746e65))   /* itne */
 
 #include "eal_private.h"
 
@@ -110,6 +114,18 @@  get_tsc_freq_arch(void)
 	uint8_t mult, model;
 	int32_t ret;
 
+#ifdef RTE_TOOLCHAIN_MSVC
+	__cpuid(cpuinfo, 0);
+	a = cpuinfo[0];
+	b = cpuinfo[1];
+	c = cpuinfo[2];
+	d = cpuinfo[3];
+#else
+	__cpuid(0, a, b, c, d);
+#endif
+	if (x86_vendor_amd(b, c, d))
+		return 0;
+
 	/*
 	 * Time Stamp Counter and Nominal Core Crystal Clock
 	 * Information Leaf