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GET /api/patches/139889/?format=api
{ "id": 139889, "url": "http://patchwork.dpdk.org/api/patches/139889/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240506114419.966498-12-igozlan@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240506114419.966498-12-igozlan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240506114419.966498-12-igozlan@nvidia.com", "date": "2024-05-06T11:44:15", "name": "[v2,12/16] net/mlx5/hws: dw order optimization code enhancement", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "40fa9cab54dc3b8cef16af184ef3871a1f483217", "submitter": { "id": 3118, "url": "http://patchwork.dpdk.org/api/people/3118/?format=api", "name": "Itamar Gozlan", "email": "igozlan@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240506114419.966498-12-igozlan@nvidia.com/mbox/", "series": [ { "id": 31885, "url": "http://patchwork.dpdk.org/api/series/31885/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31885", "date": "2024-05-06T11:44:04", "name": "[v2,01/16] net/mlx5/hws: move warn into debug level when needed", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31885/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139889/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/139889/checks/", "tags": {}, "related": [], "headers": { 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<dsosnowski@nvidia.com>, Ori Kam\n <orika@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <stable@dpdk.org>", "Subject": "[v2 12/16] net/mlx5/hws: dw order optimization code enhancement", "Date": "Mon, 6 May 2024 14:44:15 +0300", "Message-ID": "<20240506114419.966498-12-igozlan@nvidia.com>", "X-Mailer": "git-send-email 2.39.3", "In-Reply-To": "<20240506114419.966498-1-igozlan@nvidia.com>", "References": "<20240314114220.203241-1-igozlan@nvidia.com>\n <20240506114419.966498-1-igozlan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000E9D8:EE_|IA1PR12MB6387:EE_", "X-MS-Office365-Filtering-Correlation-Id": "71a644f3-4a30-4b87-76e9-08dc6dc1fe91", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", 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"dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Improving code readability by following code styles such as mlx5dr prefix\nand extracting a support check to an external function call.\nAlso, reducing unneeded static memory allocation using a bounded size\nmacro.\n\nFixes: 88ff41793e7a (\"net/mlx5/hws: reorder STE fields to improve hash\")\nCc: stable@dpdk.org\n\nSigned-off-by: Itamar Gozlan <igozlan@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 39 ++++++++++++++-------------\n 1 file changed, 20 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 81d0e0e6df..cffbb7b589 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -31,6 +31,8 @@\n \n #define MLX5DR_DEFINER_QUOTA_BLOCK 0\n #define MLX5DR_DEFINER_QUOTA_PASS 2\n+#define MLX5DR_DEFINER_MAX_ROW_LOG 32\n+#define MLX5DR_DEFINER_HL_OPT_MAX 2\n \n /* Setter function based on bit offset and mask, for 32bit DW*/\n #define _DR_SET_32(p, v, byte_off, bit_off, mask) \\\n@@ -104,21 +106,13 @@\n \t__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \\\n \t__mlx5_mask(typ, fld))\n \n-#define MAX_ROW_LOG 31\n-\n-enum header_layout {\n-\tMLX5DR_HL_IPV4_SRC = 64,\n-\tMLX5DR_HL_IPV4_DST = 65,\n-\tMAX_HL_PRIO,\n-};\n-\n /* Each row (i) indicates a different matcher size, and each column (j)\n * represents {DW5, DW4, DW3, DW2, DW1, DW0}.\n- * For values 0,..,2^i, and j (DW) 0,..,5: optimal_dist_dw[i][j] is 1 if the\n+ * For values 0,..,2^i, and j (DW) 0,..,5: mlx5dr_optimal_dist_dw[i][j] is 1 if the\n * number of different hash results on these values equals 2^i, meaning this\n * DW hash distribution is complete.\n */\n-int optimal_dist_dw[MAX_ROW_LOG][DW_SELECTORS_MATCH] = {\n+int mlx5dr_optimal_dist_dw[MLX5DR_DEFINER_MAX_ROW_LOG][DW_SELECTORS_MATCH] = {\n \t{1, 1, 1, 1, 1, 1}, {0, 1, 1, 0, 1, 0}, {0, 1, 1, 0, 1, 0},\n \t{1, 0, 1, 0, 1, 0}, {0, 0, 0, 1, 1, 0}, {0, 1, 1, 0, 1, 0},\n \t{0, 0, 0, 0, 1, 0}, {0, 1, 1, 0, 1, 0}, {0, 0, 0, 0, 0, 0},\n@@ -3471,16 +3465,16 @@ mlx5dr_definer_find_best_range_fit(struct mlx5dr_definer *definer,\n \n static void mlx5dr_definer_optimize_order(struct mlx5dr_definer *definer, int num_log)\n {\n-\tuint8_t hl_prio[MAX_HL_PRIO - 1] = {MLX5DR_HL_IPV4_SRC,\n-\t\t\t\t\t MLX5DR_HL_IPV4_DST,\n-\t\t\t\t\t MAX_HL_PRIO};\n+\tuint8_t hl_prio[MLX5DR_DEFINER_HL_OPT_MAX];\n \tint dw = 0, i = 0, j;\n \tint *dw_flag;\n \tuint8_t tmp;\n \n-\tdw_flag = optimal_dist_dw[num_log];\n+\tdw_flag = mlx5dr_optimal_dist_dw[num_log];\n+\thl_prio[0] = __mlx5_dw_off(definer_hl, ipv4_src_dest_outer.source_address);\n+\thl_prio[1] = __mlx5_dw_off(definer_hl, ipv4_src_dest_outer.destination_address);\n \n-\twhile (hl_prio[i] != MAX_HL_PRIO) {\n+\twhile (i < MLX5DR_DEFINER_HL_OPT_MAX) {\n \t\tj = 0;\n \t\t/* Finding a candidate to improve its hash distribution */\n \t\twhile (j < DW_SELECTORS_MATCH && (hl_prio[i] != definer->dw_selector[j]))\n@@ -3632,6 +3626,16 @@ int mlx5dr_definer_compare(struct mlx5dr_definer *definer_a,\n \treturn 0;\n }\n \n+static int\n+mlx5dr_definer_optimize_order_supported(struct mlx5dr_definer *match_definer,\n+\t\t\t\t\tstruct mlx5dr_matcher *matcher)\n+{\n+\treturn !mlx5dr_definer_is_jumbo(match_definer) &&\n+\t !mlx5dr_matcher_req_fw_wqe(matcher) &&\n+\t !mlx5dr_matcher_is_resizable(matcher) &&\n+\t !mlx5dr_matcher_is_insert_by_idx(matcher);\n+}\n+\n static int\n mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher,\n \t\t\t struct mlx5dr_definer *match_definer,\n@@ -3693,10 +3697,7 @@ mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher,\n \t\tgoto free_fc;\n \t}\n \n-\tif (!mlx5dr_definer_is_jumbo(match_definer) &&\n-\t !mlx5dr_matcher_req_fw_wqe(matcher) &&\n-\t !mlx5dr_matcher_is_resizable(matcher) &&\n-\t !mlx5dr_matcher_is_insert_by_idx(matcher))\n+\tif (mlx5dr_definer_optimize_order_supported(match_definer, matcher))\n \t\tmlx5dr_definer_optimize_order(match_definer, matcher->attr.rule.num_log);\n \n \t/* Find the range definer layout for match templates fcrs */\n", "prefixes": [ "v2", "12/16" ] }