diff mbox series

[05/28] net/ice/base: add timestamp masks

Message ID	20210810025140.1698163-6-qi.z.zhang@intel.com (mailing list archive)
State	Accepted, archived
Delegated to:	Qi Zhang
Headers	show Return-Path: <dev-bounces@dpdk.org> From: Qi Zhang <qi.z.zhang@intel.com> To: qiming.yang@intel.com Cc: junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>, Vignesh Sridhar <vignesh.sridhar@intel.com> Date: Tue, 10 Aug 2021 10:51:17 +0800 Message-Id: <20210810025140.1698163-6-qi.z.zhang@intel.com> In-Reply-To: <20210810025140.1698163-1-qi.z.zhang@intel.com> References: <20210810025140.1698163-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH 05/28] net/ice/base: add timestamp masks Precedence: list Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org>
Series	ice: base code update \| expand [00/28] ice: base code update [01/28] net/ice/base: add 1588 capability probe [02/28] net/ice/base: add low level functions for device clock control [03/28] net/ice/base: add ethertype IPv6 check for dummy packet [04/28] net/ice/base: change dummy packets with VLAN [05/28] net/ice/base: add timestamp masks [06/28] net/ice/base: add clock initialization function [07/28] net/ice/base: add accessors to get/set the time reference [08/28] net/ice/base: print human-friendly PHY types [09/28] net/ice/base: implement Vernier calibration logic for E822 devices [10/28] net/ice/base: clarify comments on checking PFC mode [11/28] net/ice/base: add support for starting PHY in bypass mode [12/28] net/ice/base: add E810T check function [13/28] net/ice/base: implement firmware debug dump [14/28] net/ice/base: add new AQ description [15/28] net/ice/base: refine MAC rule adding [16/28] net/ice/base: support TC nodes PIR configuration [17/28] net/ice/base: support FDIR for GRE tunnel packet [18/28] net/ice/base: support RSS for GRE tunnel packet [19/28] net/ice/base: support FDIR for GTPU EH inner IPv6 [20/28] net/ice/base: support RSS for GTPoGRE [21/28] net/ice/base: enable NVM update reset capabilities [22/28] net/ice/base: support FDIR for GTPoGRE [23/28] net/ice/base: add RSS support for IPv4/L4 checksum [24/28] net/ice/base: enable jumbo frame support during HW init [25/28] net/ice/base: support FDIR for GTPU UL/DL with QFI fields [26/28] net/ice/base: rename and add a setter function [27/28] net/ice/base: correct spellling of word data [28/28] net/ice/base: update Max TCAM/PTG Per Profile

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Zhang, Qi Z Aug. 10, 2021, 2:51 a.m. UTC

Adding macros for shift and masking of the lower timestamp work in the
Rx flex descriptor. The LSB of the timestamp-low word indicates the
validity of the timestamp while the rest 7 bits contain the timestamp.

Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
 drivers/net/ice/base/ice_lan_tx_rx.h | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Junfeng Guo Aug. 10, 2021, 4:35 a.m. UTC | #1

> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, August 10, 2021 10:51
> To: Yang, Qiming <qiming.yang@intel.com>
> Cc: Guo, Junfeng <junfeng.guo@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Sridhar, Vignesh <vignesh.sridhar@intel.com>
> Subject: [PATCH 05/28] net/ice/base: add timestamp masks
> 
> Adding macros for shift and masking of the lower timestamp work in the
> Rx flex descriptor. The LSB of the timestamp-low word indicates the
> validity of the timestamp while the rest 7 bits contain the timestamp.
> 
> Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
>  drivers/net/ice/base/ice_lan_tx_rx.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> --
> 2.26.2

Acked-by: Junfeng Guo <junfeng.guo@intel.com>

Regards,
Junfeng Guo

diff mbox series

Patch

diff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h
index 696c6a30ae..4255e9963e 100644
--- a/drivers/net/ice/base/ice_lan_tx_rx.h
+++ b/drivers/net/ice/base/ice_lan_tx_rx.h
@@ -879,6 +879,14 @@  enum ice_rx_flex_desc_exstat_bits {
 	ICE_RX_FLEX_DESC_EXSTAT_OVERSIZE_S = 3,
 };
 
+/* For ice_32b_rx_flex_desc.ts_low:
+ * [0]: Timestamp-low validity bit
+ * [1:7]: Timestamp-low value
+ */
+#define ICE_RX_FLEX_DESC_TS_L_VALID_S	0x01
+#define ICE_RX_FLEX_DESC_TS_L_VALID_M	ICE_RX_FLEX_DESC_TS_L_VALID_S
+#define ICE_RX_FLEX_DESC_TS_L_M		0xFE
+
 #define ICE_RXQ_CTX_SIZE_DWORDS		8
 #define ICE_RXQ_CTX_SZ			(ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))
 #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS	22