@@ -448,1375 +448,6 @@ static void ice_ptp_clean_cmd(struct ice_hw *hw)
ice_flush(hw);
}
-/* 56G PHY access functions */
-static const u32 eth56g_port_base[ICE_NUM_PHY_PORTS] = {
- ICE_PHY0_BASE,
- ICE_PHY1_BASE,
- ICE_PHY2_BASE,
- ICE_PHY3_BASE,
- ICE_PHY4_BASE,
-};
-
-/**
- * ice_write_phy_eth56g_raw_lp - Write a PHY port register with lock parameter
- * @hw: pointer to the HW struct
- * @reg_addr: PHY register address
- * @val: Value to write
- * @lock_sbq: true to lock the sideband queue
- */
-static enum ice_status
-ice_write_phy_eth56g_raw_lp(struct ice_hw *hw, u32 reg_addr, u32 val,
- bool lock_sbq)
-{
- struct ice_sbq_msg_input phy_msg;
- enum ice_status status;
-
- phy_msg.opcode = ice_sbq_msg_wr;
-
- phy_msg.msg_addr_low = ICE_LO_WORD(reg_addr);
- phy_msg.msg_addr_high = ICE_HI_WORD(reg_addr);
-
- phy_msg.data = val;
- phy_msg.dest_dev = phy_56g;
-
- status = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq);
-
- if (status)
- ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
- status);
-
- return status;
-}
-
-/**
- * ice_read_phy_eth56g_raw_lp - Read a PHY port register with lock parameter
- * @hw: pointer to the HW struct
- * @reg_addr: PHY port register address
- * @val: Pointer to the value to read (out param)
- * @lock_sbq: true to lock the sideband queue
- */
-static enum ice_status
-ice_read_phy_eth56g_raw_lp(struct ice_hw *hw, u32 reg_addr, u32 *val,
- bool lock_sbq)
-{
- struct ice_sbq_msg_input phy_msg;
- enum ice_status status;
-
- phy_msg.opcode = ice_sbq_msg_rd;
-
- phy_msg.msg_addr_low = ICE_LO_WORD(reg_addr);
- phy_msg.msg_addr_high = ICE_HI_WORD(reg_addr);
-
- phy_msg.dest_dev = phy_56g;
-
- status = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq);
-
- if (status)
- ice_debug(hw, ICE_DBG_PTP, "PTP failed to send msg to phy %d\n",
- status);
- else
- *val = phy_msg.data;
-
- return status;
-}
-
-/**
- * ice_phy_port_reg_address_eth56g - Calculate a PHY port register address
- * @port: Port number to be written
- * @offset: Offset from PHY port register base
- * @address: The result address
- */
-static enum ice_status
-ice_phy_port_reg_address_eth56g(u8 port, u16 offset, u32 *address)
-{
- u8 phy, lane;
-
- if (port >= ICE_NUM_EXTERNAL_PORTS)
- return ICE_ERR_OUT_OF_RANGE;
-
- phy = port / ICE_PORTS_PER_QUAD;
- lane = port % ICE_PORTS_PER_QUAD;
-
- *address = offset + eth56g_port_base[phy] +
- PHY_PTP_LANE_ADDR_STEP * lane;
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_phy_port_mem_address_eth56g - Calculate a PHY port memory address
- * @port: Port number to be written
- * @offset: Offset from PHY port register base
- * @address: The result address
- */
-static enum ice_status
-ice_phy_port_mem_address_eth56g(u8 port, u16 offset, u32 *address)
-{
- u8 phy, lane;
-
- if (port >= ICE_NUM_EXTERNAL_PORTS)
- return ICE_ERR_OUT_OF_RANGE;
-
- phy = port / ICE_PORTS_PER_QUAD;
- lane = port % ICE_PORTS_PER_QUAD;
-
- *address = offset + eth56g_port_base[phy] +
- PHY_PTP_MEM_START + PHY_PTP_MEM_LANE_STEP * lane;
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_write_phy_reg_eth56g_lp - Write a PHY port register with lock parameter
- * @hw: pointer to the HW struct
- * @port: Port number to be written
- * @offset: Offset from PHY port register base
- * @val: Value to write
- * @lock_sbq: true to lock the sideband queue
- */
-static enum ice_status
-ice_write_phy_reg_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset, u32 val,
- bool lock_sbq)
-{
- enum ice_status status;
- u32 reg_addr;
-
- status = ice_phy_port_reg_address_eth56g(port, offset, ®_addr);
- if (status)
- return status;
-
- return ice_write_phy_eth56g_raw_lp(hw, reg_addr, val, lock_sbq);
-}
-
-/**
- * ice_write_phy_reg_eth56g - Write a PHY port register with sbq locked
- * @hw: pointer to the HW struct
- * @port: Port number to be written
- * @offset: Offset from PHY port register base
- * @val: Value to write
- */
-enum ice_status
-ice_write_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val)
-{
- return ice_write_phy_reg_eth56g_lp(hw, port, offset, val, true);
-}
-
-/**
- * ice_read_phy_reg_eth56g_lp - Read a PHY port register with
- * lock parameter
- * @hw: pointer to the HW struct
- * @port: Port number to be read
- * @offset: Offset from PHY port register base
- * @val: Pointer to the value to read (out param)
- * @lock_sbq: true to lock the sideband queue
- */
-static enum ice_status
-ice_read_phy_reg_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset, u32 *val,
- bool lock_sbq)
-{
- enum ice_status status;
- u32 reg_addr;
-
- status = ice_phy_port_reg_address_eth56g(port, offset, ®_addr);
- if (status)
- return status;
-
- return ice_read_phy_eth56g_raw_lp(hw, reg_addr, val, lock_sbq);
-}
-
-/**
- * ice_read_phy_reg_eth56g - Read a PHY port register with sbq locked
- * @hw: pointer to the HW struct
- * @port: Port number to be read
- * @offset: Offset from PHY port register base
- * @val: Pointer to the value to read (out param)
- */
-enum ice_status
-ice_read_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
-{
- return ice_read_phy_reg_eth56g_lp(hw, port, offset, val, true);
-}
-
-/**
- * ice_phy_port_mem_read_eth56g_lp - Read a PHY port memory location
- * with lock parameter
- * @hw: pointer to the HW struct
- * @port: Port number to be read
- * @offset: Offset from PHY port register base
- * @val: Pointer to the value to read (out param)
- * @lock_sbq: true to lock the sideband queue
- */
-static enum ice_status
-ice_phy_port_mem_read_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset,
- u32 *val, bool lock_sbq)
-{
- enum ice_status status;
- u32 mem_addr;
-
- status = ice_phy_port_mem_address_eth56g(port, offset, &mem_addr);
- if (status)
- return status;
-
- return ice_read_phy_eth56g_raw_lp(hw, mem_addr, val, lock_sbq);
-}
-
-/**
- * ice_phy_port_mem_read_eth56g - Read a PHY port memory location with
- * sbq locked
- * @hw: pointer to the HW struct
- * @port: Port number to be read
- * @offset: Offset from PHY port register base
- * @val: Pointer to the value to read (out param)
- */
-static enum ice_status
-ice_phy_port_mem_read_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val)
-{
- return ice_phy_port_mem_read_eth56g_lp(hw, port, offset, val, true);
-}
-
-/**
- * ice_phy_port_mem_write_eth56g_lp - Write a PHY port memory location with
- * lock parameter
- * @hw: pointer to the HW struct
- * @port: Port number to be read
- * @offset: Offset from PHY port register base
- * @val: Pointer to the value to read (out param)
- * @lock_sbq: true to lock the sideband queue
- */
-static enum ice_status
-ice_phy_port_mem_write_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset,
- u32 val, bool lock_sbq)
-{
- enum ice_status status;
- u32 mem_addr;
-
- status = ice_phy_port_mem_address_eth56g(port, offset, &mem_addr);
- if (status)
- return status;
-
- return ice_write_phy_eth56g_raw_lp(hw, mem_addr, val, lock_sbq);
-}
-
-/**
- * ice_phy_port_mem_write_eth56g - Write a PHY port memory location with
- * sbq locked
- * @hw: pointer to the HW struct
- * @port: Port number to be read
- * @offset: Offset from PHY port register base
- * @val: Pointer to the value to read (out param)
- */
-static enum ice_status
-ice_phy_port_mem_write_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val)
-{
- return ice_phy_port_mem_write_eth56g_lp(hw, port, offset, val, true);
-}
-
-/**
- * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register
- * @low_addr: the low address to check
- *
- * Checks if the provided low address is one of the known 64bit PHY values
- * represented as two 32bit registers.
- */
-static bool ice_is_64b_phy_reg_eth56g(u16 low_addr)
-{
- switch (low_addr) {
- case PHY_REG_TX_TIMER_INC_PRE_L:
- case PHY_REG_RX_TIMER_INC_PRE_L:
- case PHY_REG_TX_CAPTURE_L:
- case PHY_REG_RX_CAPTURE_L:
- case PHY_REG_TOTAL_TX_OFFSET_L:
- case PHY_REG_TOTAL_RX_OFFSET_L:
- return true;
- default:
- return false;
- }
-}
-
-/**
- * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register
- * @low_addr: the low address to check
- *
- * Checks if the provided low address is one of the known 40bit PHY values
- * split into two registers with the lower 8 bits in the low register and the
- * upper 32 bits in the high register.
- */
-static bool ice_is_40b_phy_reg_eth56g(u16 low_addr)
-{
- switch (low_addr) {
- case PHY_REG_TIMETUS_L:
- return true;
- default:
- return false;
- }
-}
-
-/**
- * ice_read_40b_phy_reg_eth56g - Read a 40bit value from PHY registers
- * @hw: pointer to the HW struct
- * @port: PHY port to read from
- * @low_addr: offset of the lower register to read from
- * @val: on return, the contents of the 40bit value from the PHY registers
- *
- * Reads the two registers associated with a 40bit value and returns it in the
- * val pointer.
- * This function checks that the caller has specified a known 40 bit register
- * offset
- */
-static enum ice_status
-ice_read_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
-{
- u16 high_addr = low_addr + sizeof(u32);
- enum ice_status status;
- u32 lo, hi;
-
- if (!ice_is_40b_phy_reg_eth56g(low_addr))
- return ICE_ERR_PARAM;
-
- status = ice_read_phy_reg_eth56g(hw, port, low_addr, &lo);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, status %d",
- (int)low_addr, status);
- return status;
- }
-
- status = ice_read_phy_reg_eth56g(hw, port, low_addr + sizeof(u32), &hi);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %08x\n, status %d",
- high_addr, status);
- return status;
- }
-
- *val = ((u64)hi << P_REG_40B_HIGH_S) | (lo & P_REG_40B_LOW_M);
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers
- * @hw: pointer to the HW struct
- * @port: PHY port to read from
- * @low_addr: offset of the lower register to read from
- * @val: on return, the contents of the 64bit value from the PHY registers
- *
- * Reads the two registers associated with a 64bit value and returns it in the
- * val pointer.
- * This function checks that the caller has specified a known 64 bit register
- * offset
- */
-static enum ice_status
-ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)
-{
- u16 high_addr = low_addr + sizeof(u32);
- enum ice_status status;
- u32 lo, hi;
-
- if (!ice_is_64b_phy_reg_eth56g(low_addr))
- return ICE_ERR_PARAM;
-
- status = ice_read_phy_reg_eth56g(hw, port, low_addr, &lo);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register %#08x\n, status %d",
- low_addr, status);
- return status;
- }
-
- status = ice_read_phy_reg_eth56g(hw, port, high_addr, &hi);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register %#08x\n, status %d",
- high_addr, status);
- return status;
- }
-
- *val = ((u64)hi << 32) | lo;
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY
- * @hw: pointer to the HW struct
- * @port: port to write to
- * @low_addr: offset of the low register
- * @val: 40b value to write
- *
- * Write the provided 40b value to the two associated registers by splitting
- * it up into two chunks, the lower 8 bits and the upper 32 bits.
- * This function checks that the caller has specified a known 40 bit register
- * offset
- */
-static enum ice_status
-ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
-{
- u16 high_addr = low_addr + sizeof(u32);
- enum ice_status status;
- u32 lo, hi;
-
- if (!ice_is_40b_phy_reg_eth56g(low_addr))
- return ICE_ERR_PARAM;
-
- lo = (u32)(val & P_REG_40B_LOW_M);
- hi = (u32)(val >> P_REG_40B_HIGH_S);
-
- status = ice_write_phy_reg_eth56g(hw, port, low_addr, lo);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d",
- low_addr, status);
- return status;
- }
-
- status = ice_write_phy_reg_eth56g(hw, port, high_addr, hi);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d",
- high_addr, status);
- return status;
- }
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers
- * @hw: pointer to the HW struct
- * @port: PHY port to read from
- * @low_addr: offset of the lower register to read from
- * @val: the contents of the 64bit value to write to PHY
- *
- * Write the 64bit value to the two associated 32bit PHY registers.
- * This function checks that the caller has specified a known 64 bit register
- * offset
- */
-static enum ice_status
-ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)
-{
- u16 high_addr = low_addr + sizeof(u32);
- enum ice_status status;
- u32 lo, hi;
-
- if (!ice_is_64b_phy_reg_eth56g(low_addr))
- return ICE_ERR_PARAM;
-
- lo = ICE_LO_DWORD(val);
- hi = ICE_HI_DWORD(val);
-
- status = ice_write_phy_reg_eth56g(hw, port, low_addr, lo);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, status %d",
- low_addr, status);
- return status;
- }
-
- status = ice_write_phy_reg_eth56g(hw, port, high_addr, hi);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, status %d",
- high_addr, status);
- return status;
- }
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_read_phy_tstamp_eth56g - Read a PHY timestamp out of the port memory
- * @hw: pointer to the HW struct
- * @port: the port to read from
- * @idx: the timestamp index to read
- * @tstamp: on return, the 40bit timestamp value
- *
- * Read a 40bit timestamp value out of the two associated entries in the
- * port memory block of the internal PHYs of the 56G devices.
- */
-static enum ice_status
-ice_read_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, u64 *tstamp)
-{
- enum ice_status status;
- u16 lo_addr, hi_addr;
- u32 lo, hi;
-
- lo_addr = (u16)PHY_TSTAMP_L(idx);
- hi_addr = (u16)PHY_TSTAMP_U(idx);
-
- status = ice_phy_port_mem_read_eth56g(hw, port, lo_addr, &lo);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, status %d\n",
- status);
- return status;
- }
-
- status = ice_phy_port_mem_read_eth56g(hw, port, hi_addr, &hi);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, status %d\n",
- status);
- return status;
- }
-
- /* For 56G based internal PHYs, the timestamp is reported with the
- * lower 8 bits in the low register, and the upper 32 bits in the high
- * register.
- */
- *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M);
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_clear_phy_tstamp_eth56g - Clear a timestamp from the quad block
- * @hw: pointer to the HW struct
- * @port: the quad to read from
- * @idx: the timestamp index to reset
- *
- * Clear a timestamp, resetting its valid bit, in the PHY port memory of
- * internal PHYs of the 56G devices.
- */
-static enum ice_status
-ice_clear_phy_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx)
-{
- enum ice_status status;
- u16 lo_addr;
-
- lo_addr = (u16)PHY_TSTAMP_L(idx);
-
- status = ice_phy_port_mem_write_eth56g(hw, port, lo_addr, 0);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, status %d\n",
- status);
- return status;
- }
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_prep_port_phy_time_eth56g - Prepare one PHY port with initial time
- * @hw: pointer to the HW struct
- * @port: port number
- * @phy_time: time to initialize the PHY port clocks to
- *
- * Write a new initial time value into registers of a specific PHY port.
- */
-static enum ice_status
-ice_ptp_prep_port_phy_time_eth56g(struct ice_hw *hw, u8 port, u64 phy_time)
-{
- enum ice_status status;
-
- /* Tx case */
- status = ice_write_64b_phy_reg_eth56g(hw, port,
- PHY_REG_TX_TIMER_INC_PRE_L,
- phy_time);
- if (status)
- return status;
-
- /* Rx case */
- return ice_write_64b_phy_reg_eth56g(hw, port,
- PHY_REG_RX_TIMER_INC_PRE_L,
- phy_time);
-}
-
-/**
- * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time
- * @hw: pointer to the HW struct
- * @time: Time to initialize the PHY port clocks to
- *
- * Program the PHY port registers with a new initial time value. The port
- * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync
- * command. The time value is the upper 32 bits of the PHY timer, usually in
- * units of nominal nanoseconds.
- */
-static enum ice_status
-ice_ptp_prep_phy_time_eth56g(struct ice_hw *hw, u32 time)
-{
- enum ice_status status;
- u64 phy_time;
- u8 port;
-
- /* The time represents the upper 32 bits of the PHY timer, so we need
- * to shift to account for this when programming.
- */
- phy_time = (u64)time << 32;
-
- for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
- if (!(hw->ena_lports & BIT(port)))
- continue;
- status = ice_ptp_prep_port_phy_time_eth56g(hw, port,
- phy_time);
-
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, status %d\n",
- port, status);
- return status;
- }
- }
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust
- * @hw: pointer to HW struct
- * @port: Port number to be programmed
- * @time: time in cycles to adjust the port Tx and Rx clocks
- * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the
- * sq_lock has already been locked at a higher level
- *
- * Program the port for an atomic adjustment by writing the Tx and Rx timer
- * registers. The atomic adjustment won't be completed until the driver issues
- * an ICE_PTP_ADJ_TIME command.
- *
- * Note that time is not in units of nanoseconds. It is in clock time
- * including the lower sub-nanosecond portion of the port timer.
- *
- * Negative adjustments are supported using 2s complement arithmetic.
- */
-enum ice_status
-ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time,
- bool lock_sbq)
-{
- enum ice_status status;
- u32 l_time, u_time;
-
- l_time = ICE_LO_DWORD(time);
- u_time = ICE_HI_DWORD(time);
-
- /* Tx case */
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_TX_TIMER_INC_PRE_L,
- l_time, lock_sbq);
- if (status)
- goto exit_err;
-
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_TX_TIMER_INC_PRE_U,
- u_time, lock_sbq);
- if (status)
- goto exit_err;
-
- /* Rx case */
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_RX_TIMER_INC_PRE_L,
- l_time, lock_sbq);
- if (status)
- goto exit_err;
-
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_RX_TIMER_INC_PRE_U,
- u_time, lock_sbq);
- if (status)
- goto exit_err;
-
- return ICE_SUCCESS;
-
-exit_err:
- ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, status %d\n",
- port, status);
- return status;
-}
-
-/**
- * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment
- * @hw: pointer to HW struct
- * @adj: adjustment in nanoseconds
- * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the
- * sq_lock has already been locked at a higher level
- *
- * Prepare the PHY ports for an atomic time adjustment by programming the PHY
- * Tx and Rx port registers. The actual adjustment is completed by issuing an
- * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.
- */
-static enum ice_status
-ice_ptp_prep_phy_adj_eth56g(struct ice_hw *hw, s32 adj, bool lock_sbq)
-{
- enum ice_status status = ICE_SUCCESS;
- s64 cycles;
- u8 port;
-
- /* The port clock supports adjustment of the sub-nanosecond portion of
- * the clock. We shift the provided adjustment in nanoseconds to
- * calculate the appropriate adjustment to program into the PHY ports.
- */
- cycles = (s64)adj << 32;
-
- for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
- if (!(hw->ena_lports & BIT(port)))
- continue;
-
- status = ice_ptp_prep_port_adj_eth56g(hw, port, cycles,
- lock_sbq);
- if (status)
- break;
- }
-
- return status;
-}
-
-/**
- * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment
- * @hw: pointer to HW struct
- * @incval: new increment value to prepare
- *
- * Prepare each of the PHY ports for a new increment value by programming the
- * port's TIMETUS registers. The new increment value will be updated after
- * issuing an ICE_PTP_INIT_INCVAL command.
- */
-static enum ice_status
-ice_ptp_prep_phy_incval_eth56g(struct ice_hw *hw, u64 incval)
-{
- enum ice_status status;
- u8 port;
-
- for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
- if (!(hw->ena_lports & BIT(port)))
- continue;
- status = ice_write_40b_phy_reg_eth56g(hw, port,
- PHY_REG_TIMETUS_L,
- incval);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, status %d\n",
- port, status);
- return status;
- }
- }
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_read_phy_incval_eth56g - Read a PHY port's current incval
- * @hw: pointer to the HW struct
- * @port: the port to read
- * @incval: on return, the time_clk_cyc incval for this port
- *
- * Read the time_clk_cyc increment value for a given PHY port.
- */
-enum ice_status
-ice_ptp_read_phy_incval_eth56g(struct ice_hw *hw, u8 port, u64 *incval)
-{
- enum ice_status status;
-
- status = ice_read_40b_phy_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
- incval);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read TIMETUS_L, status %d\n",
- status);
- return status;
- }
-
- ice_debug(hw, ICE_DBG_PTP, "read INCVAL = 0x%016llx\n",
- (unsigned long long)*incval);
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_prep_phy_adj_target_eth56g - Prepare PHY for adjust at target time
- * @hw: pointer to HW struct
- * @target_time: target time to program
- *
- * Program the PHY port Tx and Rx TIMER_CNT_ADJ registers used for the
- * ICE_PTP_ADJ_TIME_AT_TIME command. This should be used in conjunction with
- * ice_ptp_prep_phy_adj_eth56g to program an atomic adjustment that is
- * delayed until a specified target time.
- *
- * Note that a target time adjustment is not currently supported on E810
- * devices.
- */
-static enum ice_status
-ice_ptp_prep_phy_adj_target_eth56g(struct ice_hw *hw, u32 target_time)
-{
- enum ice_status status;
- u8 port;
-
- for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
- if (!(hw->ena_lports & BIT(port)))
- continue;
-
- /* Tx case */
- /* No sub-nanoseconds data */
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_TX_TIMER_CNT_ADJ_L,
- 0, true);
- if (status)
- goto exit_err;
-
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_TX_TIMER_CNT_ADJ_U,
- target_time, true);
- if (status)
- goto exit_err;
-
- /* Rx case */
- /* No sub-nanoseconds data */
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_RX_TIMER_CNT_ADJ_L,
- 0, true);
- if (status)
- goto exit_err;
-
- status = ice_write_phy_reg_eth56g_lp(hw, port,
- PHY_REG_RX_TIMER_CNT_ADJ_U,
- target_time, true);
- if (status)
- goto exit_err;
- }
-
- return ICE_SUCCESS;
-
-exit_err:
- ice_debug(hw, ICE_DBG_PTP, "Failed to write target time for port %u, status %d\n",
- port, status);
-
- return status;
-}
-
-/**
- * ice_ptp_read_port_capture_eth56g - Read a port's local time capture
- * @hw: pointer to HW struct
- * @port: Port number to read
- * @tx_ts: on return, the Tx port time capture
- * @rx_ts: on return, the Rx port time capture
- *
- * Read the port's Tx and Rx local time capture values.
- */
-enum ice_status
-ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, u64 *tx_ts,
- u64 *rx_ts)
-{
- enum ice_status status;
-
- /* Tx case */
- status = ice_read_64b_phy_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L,
- tx_ts);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, status %d\n",
- status);
- return status;
- }
-
- ice_debug(hw, ICE_DBG_PTP, "tx_init = %#016llx\n",
- (unsigned long long)*tx_ts);
-
- /* Rx case */
- status = ice_read_64b_phy_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L,
- rx_ts);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, status %d\n",
- status);
- return status;
- }
-
- ice_debug(hw, ICE_DBG_PTP, "rx_init = %#016llx\n",
- (unsigned long long)*rx_ts);
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_one_port_cmd_eth56g - Prepare a single PHY port for a timer command
- * @hw: pointer to HW struct
- * @port: Port to which cmd has to be sent
- * @cmd: Command to be sent to the port
- * @lock_sbq: true if the sideband queue lock must be acquired
- *
- * Prepare the requested port for an upcoming timer sync command.
- */
-enum ice_status
-ice_ptp_one_port_cmd_eth56g(struct ice_hw *hw, u8 port,
- enum ice_ptp_tmr_cmd cmd, bool lock_sbq)
-{
- enum ice_status status;
- u32 cmd_val, val;
- u8 tmr_idx;
-
- tmr_idx = ice_get_ptp_src_clock_index(hw);
- cmd_val = tmr_idx << SEL_PHY_SRC;
- switch (cmd) {
- case ICE_PTP_INIT_TIME:
- cmd_val |= PHY_CMD_INIT_TIME;
- break;
- case ICE_PTP_INIT_INCVAL:
- cmd_val |= PHY_CMD_INIT_INCVAL;
- break;
- case ICE_PTP_ADJ_TIME:
- cmd_val |= PHY_CMD_ADJ_TIME;
- break;
- case ICE_PTP_ADJ_TIME_AT_TIME:
- cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME;
- break;
- case ICE_PTP_READ_TIME:
- cmd_val |= PHY_CMD_READ_TIME;
- break;
- default:
- ice_warn(hw, "Unknown timer command %u\n", cmd);
- return ICE_ERR_PARAM;
- }
-
- /* Tx case */
- /* Read, modify, write */
- status = ice_read_phy_reg_eth56g_lp(hw, port, PHY_REG_TX_TMR_CMD, &val,
- lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, status %d\n",
- status);
- return status;
- }
-
- /* Modify necessary bits only and perform write */
- val &= ~TS_CMD_MASK;
- val |= cmd_val;
-
- status = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_TX_TMR_CMD, val,
- lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, status %d\n",
- status);
- return status;
- }
-
- /* Rx case */
- /* Read, modify, write */
- status = ice_read_phy_reg_eth56g_lp(hw, port, PHY_REG_RX_TMR_CMD, &val,
- lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, status %d\n",
- status);
- return status;
- }
-
- /* Modify necessary bits only and perform write */
- val &= ~TS_CMD_MASK;
- val |= cmd_val;
-
- status = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_RX_TMR_CMD, val,
- lock_sbq);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, status %d\n",
- status);
- return status;
- }
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_port_cmd_eth56g - Prepare all ports for a timer command
- * @hw: pointer to the HW struct
- * @cmd: timer command to prepare
- * @lock_sbq: true if the sideband queue lock must be acquired
- *
- * Prepare all ports connected to this device for an upcoming timer sync
- * command.
- */
-static enum ice_status
-ice_ptp_port_cmd_eth56g(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,
- bool lock_sbq)
-{
- enum ice_status status;
- u8 port;
-
- for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {
- if (!(hw->ena_lports & BIT(port)))
- continue;
-
- status = ice_ptp_one_port_cmd_eth56g(hw, port, cmd, lock_sbq);
- if (status)
- return status;
- }
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_calc_fixed_tx_offset_eth56g - Calculated Fixed Tx offset for a port
- * @hw: pointer to the HW struct
- * @link_spd: the Link speed to calculate for
- *
- * Calculate the fixed offset due to known static latency data.
- */
-static u64
-ice_calc_fixed_tx_offset_eth56g(struct ice_hw *hw,
- enum ice_ptp_link_spd link_spd)
-{
- u64 fixed_offset = 0;
- return fixed_offset;
-}
-
-/**
- * ice_phy_cfg_tx_offset_eth56g - Configure total Tx timestamp offset
- * @hw: pointer to the HW struct
- * @port: the PHY port to configure
- *
- * Program the PHY_REG_TOTAL_TX_OFFSET register with the total number of TUs to
- * adjust Tx timestamps by.
- *
- * To avoid overflow, when calculating the offset based on the known static
- * latency values, we use measurements in 1/100th of a nanosecond, and divide
- * the TUs per second up front. This avoids overflow while allowing
- * calculation of the adjustment using integer arithmetic.
- */
-enum ice_status ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port)
-{
- enum ice_ptp_link_spd link_spd = ICE_PTP_LNK_SPD_10G;
- enum ice_status status;
- u64 total_offset;
-
- total_offset = ice_calc_fixed_tx_offset_eth56g(hw, link_spd);
-
- /* Now that the total offset has been calculated, program it to the
- * PHY and indicate that the Tx offset is ready. After this,
- * timestamps will be enabled.
- */
- status = ice_write_64b_phy_reg_eth56g(hw, port,
- PHY_REG_TOTAL_TX_OFFSET_L,
- total_offset);
- if (status)
- return status;
-
- return ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1);
-}
-
-/**
- * ice_calc_fixed_rx_offset_eth56g - Calculated the fixed Rx offset for a port
- * @hw: pointer to HW struct
- * @link_spd: The Link speed to calculate for
- *
- * Determine the fixed Rx latency for a given link speed.
- */
-static u64
-ice_calc_fixed_rx_offset_eth56g(struct ice_hw *hw,
- enum ice_ptp_link_spd link_spd)
-{
- u64 fixed_offset = 0;
- return fixed_offset;
-}
-
-/**
- * ice_phy_cfg_rx_offset_eth56g - Configure total Rx timestamp offset
- * @hw: pointer to the HW struct
- * @port: the PHY port to configure
- *
- * Program the PHY_REG_TOTAL_RX_OFFSET register with the number of Time Units to
- * adjust Rx timestamps by. This combines calculations from the Vernier offset
- * measurements taken in hardware with some data about known fixed delay as
- * well as adjusting for multi-lane alignment delay.
- *
- * This function must be called only after the offset registers are valid,
- * i.e. after the Vernier calibration wait has passed, to ensure that the PHY
- * has measured the offset.
- *
- * To avoid overflow, when calculating the offset based on the known static
- * latency values, we use measurements in 1/100th of a nanosecond, and divide
- * the TUs per second up front. This avoids overflow while allowing
- * calculation of the adjustment using integer arithmetic.
- */
-enum ice_status ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port)
-{
- enum ice_status status;
- u64 total_offset;
-
- total_offset = ice_calc_fixed_rx_offset_eth56g(hw, 0);
-
- /* Now that the total offset has been calculated, program it to the
- * PHY and indicate that the Rx offset is ready. After this,
- * timestamps will be enabled.
- */
- status = ice_write_64b_phy_reg_eth56g(hw, port,
- PHY_REG_TOTAL_RX_OFFSET_L,
- total_offset);
- if (status)
- return status;
-
- return ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1);
-}
-
-/**
- * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time
- * @hw: pointer to the HW struct
- * @port: the PHY port to read
- * @phy_time: on return, the 64bit PHY timer value
- * @phc_time: on return, the lower 64bits of PHC time
- *
- * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY
- * and PHC timer values.
- */
-static enum ice_status
-ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, u64 *phy_time,
- u64 *phc_time)
-{
- enum ice_status status;
- u64 tx_time, rx_time;
- u32 zo, lo;
- u8 tmr_idx;
-
- tmr_idx = ice_get_ptp_src_clock_index(hw);
-
- /* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */
- ice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);
-
- /* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */
- status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_READ_TIME, true);
- if (status)
- return status;
-
- /* Issue the sync to start the ICE_PTP_READ_TIME capture */
- ice_ptp_exec_tmr_cmd(hw);
- ice_ptp_clean_cmd(hw);
-
- /* Read the captured PHC time from the shadow time registers */
- zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));
- lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));
- *phc_time = (u64)lo << 32 | zo;
-
- /* Read the captured PHY time from the PHY shadow registers */
- status = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time);
- if (status)
- return status;
-
- /* If the PHY Tx and Rx timers don't match, log a warning message.
- * Note that this should not happen in normal circumstances since the
- * driver always programs them together.
- */
- if (tx_time != rx_time)
- ice_warn(hw, "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n",
- port, (unsigned long long)tx_time,
- (unsigned long long)rx_time);
-
- *phy_time = tx_time;
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer
- * @hw: pointer to the HW struct
- * @port: the PHY port to synchronize
- *
- * Perform an adjustment to ensure that the PHY and PHC timers are in sync.
- * This is done by issuing a ICE_PTP_READ_TIME command which triggers a
- * simultaneous read of the PHY timer and PHC timer. Then we use the
- * difference to calculate an appropriate 2s complement addition to add
- * to the PHY timer in order to ensure it reads the same value as the
- * primary PHC timer.
- */
-static enum ice_status ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port)
-{
- u64 phc_time, phy_time, difference;
- enum ice_status status;
-
- if (!ice_ptp_lock(hw)) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n");
- return ICE_ERR_NOT_READY;
- }
-
- status = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time,
- &phc_time);
- if (status)
- goto err_unlock;
-
- /* Calculate the amount required to add to the port time in order for
- * it to match the PHC time.
- *
- * Note that the port adjustment is done using 2s complement
- * arithmetic. This is convenient since it means that we can simply
- * calculate the difference between the PHC time and the port time,
- * and it will be interpreted correctly.
- */
-
- ice_ptp_src_cmd(hw, ICE_PTP_NOP);
- difference = phc_time - phy_time;
-
- status = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference, true);
- if (status)
- goto err_unlock;
-
- status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_ADJ_TIME, true);
- if (status)
- goto err_unlock;
-
- /* Issue the sync to activate the time adjustment */
- ice_ptp_exec_tmr_cmd(hw);
- ice_ptp_clean_cmd(hw);
-
- /* Re-capture the timer values to flush the command registers and
- * verify that the time was properly adjusted.
- */
-
- status = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time,
- &phc_time);
- if (status)
- goto err_unlock;
-
- ice_info(hw, "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n",
- port, (unsigned long long)phy_time,
- (unsigned long long)phc_time);
-
-err_unlock:
- ice_ptp_unlock(hw);
- return status;
-}
-
-/**
- * ice_stop_phy_timer_eth56g - Stop the PHY clock timer
- * @hw: pointer to the HW struct
- * @port: the PHY port to stop
- * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS
- *
- * Stop the clock of a PHY port. This must be done as part of the flow to
- * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
- * initialized or when link speed changes.
- */
-enum ice_status
-ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset)
-{
- enum ice_status status;
-
- status = ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0);
- if (status)
- return status;
-
- status = ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0);
- if (status)
- return status;
-
- ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port);
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_start_phy_timer_eth56g - Start the PHY clock timer
- * @hw: pointer to the HW struct
- * @port: the PHY port to start
- * @bypass: unused, for compatibility
- *
- * Start the clock of a PHY port. This must be done as part of the flow to
- * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
- * initialized or when link speed changes.
- *
- */
-enum ice_status
-ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass)
-{
- enum ice_status status;
- u32 lo, hi;
- u64 incval;
- u8 tmr_idx;
-
- tmr_idx = ice_get_ptp_src_clock_index(hw);
-
- status = ice_stop_phy_timer_eth56g(hw, port, false);
- if (status)
- return status;
-
- ice_ptp_src_cmd(hw, ICE_PTP_NOP);
-
- lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));
- hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));
- incval = (u64)hi << 32 | lo;
-
- status = ice_write_40b_phy_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,
- incval);
- if (status)
- return status;
-
- status = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_INIT_INCVAL,
- true);
- if (status)
- return status;
-
- ice_ptp_exec_tmr_cmd(hw);
-
- status = ice_sync_phy_timer_eth56g(hw, port);
- if (status)
- return status;
-
- /* Program the Tx offset */
- status = ice_phy_cfg_tx_offset_eth56g(hw, port);
- if (status)
- return status;
-
- /* Program the Rx offset */
- status = ice_phy_cfg_rx_offset_eth56g(hw, port);
- if (status)
- return status;
-
- ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_init_phc_eth56g - Perform E822 specific PHC initialization
- * @hw: pointer to HW struct
- *
- * Perform PHC initialization steps specific to E822 devices.
- */
-static enum ice_status ice_ptp_init_phc_eth56g(struct ice_hw *hw)
-{
- enum ice_status status = ICE_SUCCESS;
- u32 regval;
-
- /* Enable reading switch and PHY registers over the sideband queue */
-#define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1)
-#define PF_SB_REM_DEV_CTL_PHY0 BIT(2)
- regval = rd32(hw, PF_SB_REM_DEV_CTL);
- regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ |
- PF_SB_REM_DEV_CTL_PHY0);
- wr32(hw, PF_SB_REM_DEV_CTL, regval);
-
- /* Initialize the Clock Generation Unit */
- status = ice_init_cgu_e822(hw);
-
- return status;
-}
-
-/**
- * ice_ptp_read_tx_hwtstamp_status_eth56g - Get the current TX timestamp
- * status mask. Returns the mask of ports where TX timestamps are available
- * @hw: pointer to the HW struct
- * @ts_status: the timestamp mask pointer
- */
-enum ice_status
-ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status)
-{
- enum ice_status status;
-
- status = ice_read_phy_eth56g_raw_lp(hw, PHY_PTP_INT_STATUS, ts_status,
- true);
- if (status)
- return status;
-
- ice_debug(hw, ICE_DBG_PTP, "PHY interrupt status: %x\n", *ts_status);
-
- return ICE_SUCCESS;
-}
-
-/**
- * ice_ptp_init_phy_cfg - Get the current TX timestamp status
- * mask. Returns the mask of ports where TX timestamps are available
- * @hw: pointer to the HW struct
- */
-enum ice_status
-ice_ptp_init_phy_cfg(struct ice_hw *hw)
-{
- enum ice_status status;
- u32 phy_rev;
-
- status = ice_read_phy_eth56g_raw_lp(hw, PHY_REG_REVISION, &phy_rev,
- true);
- if (status)
- return status;
-
- if (phy_rev == PHY_REVISION_ETH56G) {
- hw->phy_cfg = ICE_PHY_ETH56G;
- return ICE_SUCCESS;
- }
-
- if (ice_is_e810(hw))
- hw->phy_cfg = ICE_PHY_E810;
- else
- hw->phy_cfg = ICE_PHY_E822;
-
- return ICE_SUCCESS;
-}
/* ----------------------------------------------------------------------------
* E822 family functions
@@ -4891,9 +3522,6 @@ ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq)
/* Next, prepare the ports */
switch (hw->phy_cfg) {
- case ICE_PHY_ETH56G:
- status = ice_ptp_port_cmd_eth56g(hw, cmd, lock_sbq);
- break;
case ICE_PHY_E810:
status = ice_ptp_port_cmd_e810(hw, cmd, lock_sbq);
break;
@@ -4946,9 +3574,6 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time)
/* PHY Clks */
/* Fill Rx and Tx ports and send msg to PHY */
switch (hw->phy_cfg) {
- case ICE_PHY_ETH56G:
- status = ice_ptp_prep_phy_time_eth56g(hw, time & 0xFFFFFFFF);
- break;
case ICE_PHY_E810:
status = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);
break;
@@ -4991,9 +3616,6 @@ enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval));
switch (hw->phy_cfg) {
- case ICE_PHY_ETH56G:
- status = ice_ptp_prep_phy_incval_eth56g(hw, incval);
- break;
case ICE_PHY_E810:
status = ice_ptp_prep_phy_incval_e810(hw, incval);
break;
@@ -5062,9 +3684,6 @@ enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq)
wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);
switch (hw->phy_cfg) {
- case ICE_PHY_ETH56G:
- status = ice_ptp_prep_phy_adj_eth56g(hw, adj, lock_sbq);
- break;
case ICE_PHY_E810:
status = ice_ptp_prep_phy_adj_e810(hw, adj, lock_sbq);
break;
@@ -5123,9 +3742,6 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)
/* Prepare PHY port adjustments */
switch (hw->phy_cfg) {
- case ICE_PHY_ETH56G:
- status = ice_ptp_prep_phy_adj_eth56g(hw, adj, true);
- break;
case ICE_PHY_E810:
status = ice_ptp_prep_phy_adj_e810(hw, adj, true);
break;
@@ -5141,9 +3757,6 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)
/* Set target time for each PHY port */
switch (hw->phy_cfg) {
- case ICE_PHY_ETH56G:
- status = ice_ptp_prep_phy_adj_target_eth56g(hw, time_lo);
- break;
case ICE_PHY_E810:
status = ice_ptp_prep_phy_adj_target_e810(hw, time_lo);
break;
@@ -5177,9 +3790,6 @@ ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
enum ice_status status;
switch (hw->phy_cfg) {
- case ICE_PHY_ETH56G:
- status = ice_read_phy_tstamp_eth56g(hw, block, idx, tstamp);
- break;
case ICE_PHY_E810:
status = ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
break;
@@ -5209,9 +3819,6 @@ ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
enum ice_status status;
switch (hw->phy_cfg) {
- case ICE_PHY_ETH56G:
- status = ice_clear_phy_tstamp_eth56g(hw, block, idx);
- break;
case ICE_PHY_E810:
status = ice_clear_phy_tstamp_e810(hw, block, idx);
break;
@@ -5243,9 +3850,6 @@ enum ice_status ice_ptp_init_phc(struct ice_hw *hw)
(void)rd32(hw, GLTSYN_STAT(src_idx));
switch (hw->phy_cfg) {
- case ICE_PHY_ETH56G:
- status = ice_ptp_init_phc_eth56g(hw);
- break;
case ICE_PHY_E810:
status = ice_ptp_init_phc_e810(hw);
break;
@@ -235,38 +235,7 @@ bool ice_is_pca9575_present(struct ice_hw *hw);
void
ice_ptp_process_cgu_err(struct ice_hw *hw, struct ice_rq_event_info *event);
-/* ETH56G family functions */
-enum ice_status
-ice_read_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val);
-enum ice_status
-ice_write_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val);
-enum ice_status
-ice_read_phy_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val);
-enum ice_status
-ice_write_phy_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val);
-
-enum ice_status
-ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time,
- bool lock_sbq);
-
-enum ice_status
-ice_ptp_read_phy_incval_eth56g(struct ice_hw *hw, u8 port, u64 *incval);
-enum ice_status
-ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port,
- u64 *tx_ts, u64 *rx_ts);
-enum ice_status
-ice_ptp_one_port_cmd_eth56g(struct ice_hw *hw, u8 port,
- enum ice_ptp_tmr_cmd cmd, bool lock_sbq);
-enum ice_status
-ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status);
-enum ice_status
-ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset);
-enum ice_status
-ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass);
-enum ice_status ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port);
-enum ice_status ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port);
-enum ice_status ice_ptp_init_phy_cfg(struct ice_hw *hw);
#define PFTSYN_SEM_BYTES 4
@@ -528,12 +497,6 @@ enum ice_status ice_ptp_init_phy_cfg(struct ice_hw *hw);
#define ICE_E810T_SMA_MIN_BIT 3
#define ICE_E810T_SMA_MAX_BIT 7
#define ICE_E810T_P1_OFFSET 8
-/* 56G PHY quad register base addresses */
-#define ICE_PHY0_BASE 0x092000
-#define ICE_PHY1_BASE 0x126000
-#define ICE_PHY2_BASE 0x1BA000
-#define ICE_PHY3_BASE 0x24E000
-#define ICE_PHY4_BASE 0x2E2000
/* Timestamp memory */
#define PHY_PTP_LANE_ADDR_STEP 0x98
@@ -602,6 +565,5 @@ enum ice_status ice_ptp_init_phy_cfg(struct ice_hw *hw);
#define PHY_TSTAMP_U(x) (((x) * 8) + 4)
#define PHY_REG_REVISION 0x85000
-#define PHY_REVISION_ETH56G 0x10200
#endif /* _ICE_PTP_HW_H_ */