diff mbox series

[15/30] net/ice/base: allow skip main timer

Message ID 20230427062001.478032-16-qiming.yang@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Qi Zhang
Headers
Series net/ice/base: share code update |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Qiming Yang April 27, 2023, 6:19 a.m. UTC 
  Allow initialization functions to skip main timer programming.

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qiming Yang <qiming.yang@intel.com>
---
 drivers/net/ice/base/ice_ptp_hw.c | 32 ++++++++++++++++++++-----------
 drivers/net/ice/base/ice_ptp_hw.h |  9 ++++++---
 drivers/net/ice/ice_ethdev.c      |  2 +-
 3 files changed, 28 insertions(+), 15 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index 61145262ac..43b7e313f4 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -3550,6 +3550,7 @@  ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq)
  * ice_ptp_init_time - Initialize device time to provided value
  * @hw: pointer to HW struct
  * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H)
+ * @wr_main_tmr: program the main timer
  *
  * Initialize the device to the specified time provided. This requires a three
  * step process:
@@ -3559,7 +3560,8 @@  ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq)
  * 3) issue an init_time timer command to synchronously switch both the source
  *    and port timers to the new init time value at the next clock cycle.
  */
-enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time)
+enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time,
+				  bool wr_main_tmr)
 {
 	enum ice_status status;
 	u8 tmr_idx;
@@ -3567,9 +3569,11 @@  enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time)
 	tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
 
 	/* Source timers */
-	wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time));
-	wr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time));
-	wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);
+	if (wr_main_tmr) {
+		wr32(hw, GLTSYN_SHTIME_L(tmr_idx), ICE_LO_DWORD(time));
+		wr32(hw, GLTSYN_SHTIME_H(tmr_idx), ICE_HI_DWORD(time));
+		wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0);
+	}
 
 	/* PHY Clks */
 	/* Fill Rx and Tx ports and send msg to PHY */
@@ -3594,8 +3598,9 @@  enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time)
  * ice_ptp_write_incval - Program PHC with new increment value
  * @hw: pointer to HW struct
  * @incval: Source timer increment value per clock cycle
+ * @wr_main_tmr: Program the main timer
  *
- * Program the PHC with a new increment value. This requires a three-step
+ * Program the timers with a new increment value. This requires a three-step
  * process:
  *
  * 1) Write the increment value to the source timer shadow registers
@@ -3604,16 +3609,19 @@  enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time)
  *    the source and port timers to the new increment value at the next clock
  *    cycle.
  */
-enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
+enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval,
+				     bool wr_main_tmr)
 {
 	enum ice_status status;
 	u8 tmr_idx;
 
 	tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
 
-	/* Shadow Adjust */
-	wr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval));
-	wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval));
+	if (wr_main_tmr) {
+		/* Shadow Adjust */
+		wr32(hw, GLTSYN_SHADJ_L(tmr_idx), ICE_LO_DWORD(incval));
+		wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval));
+	}
 
 	switch (hw->phy_cfg) {
 	case ICE_PHY_E810:
@@ -3636,17 +3644,19 @@  enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval)
  * ice_ptp_write_incval_locked - Program new incval while holding semaphore
  * @hw: pointer to HW struct
  * @incval: Source timer increment value per clock cycle
+ * @wr_main_tmr: Program the main timer
  *
  * Program a new PHC incval while holding the PTP semaphore.
  */
-enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval)
+enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval,
+					    bool wr_main_tmr)
 {
 	enum ice_status status;
 
 	if (!ice_ptp_lock(hw))
 		return ICE_ERR_NOT_READY;
 
-	status = ice_ptp_write_incval(hw, incval);
+	status = ice_ptp_write_incval(hw, incval, wr_main_tmr);
 
 	ice_ptp_unlock(hw);
 
diff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h
index d2581e63f9..48a30f1f4e 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -131,9 +131,12 @@  u64 ice_ptp_read_src_incval(struct ice_hw *hw);
 bool ice_ptp_lock(struct ice_hw *hw);
 void ice_ptp_unlock(struct ice_hw *hw);
 void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);
-enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time);
-enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
-enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
+enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time,
+				  bool wr_main_tmr);
+enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval,
+				     bool wr_main_tmr);
+enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval,
+					    bool wr_main_tmr);
 enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq);
 enum ice_status
 ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj);
diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index 9a88cf9796..6700893bc5 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -5832,7 +5832,7 @@  ice_timesync_enable(struct rte_eth_dev *dev)
 			return -1;
 		}
 
-		ret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810);
+		ret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810, 1);
 		if (ret) {
 			PMD_DRV_LOG(ERR,
 				"Failed to write PHC increment time value");