@@ -2369,6 +2369,11 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,
true : false;
ice_debug(hw, ICE_DBG_INIT, "%s: nvm_unified_update = %d\n", prefix,
caps->nvm_unified_update);
+ caps->netlist_auth =
+ (number & ICE_NVM_MGMT_NETLIST_AUTH_SUPPORT) ?
+ true : false;
+ ice_debug(hw, ICE_DBG_INIT, "%s: netlist_auth = %d\n", prefix,
+ caps->netlist_auth);
break;
case ICE_AQC_CAPS_MAX_MTU:
caps->max_mtu = number;
@@ -3814,6 +3819,7 @@ enum ice_status
ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
struct ice_sq_cd *cd)
{
+ enum ice_status status = ICE_ERR_AQ_ERROR;
struct ice_aqc_restart_an *cmd;
struct ice_aq_desc desc;
@@ -3828,7 +3834,16 @@ ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
else
cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
- return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
+ status = ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
+ if (status)
+ return status;
+
+ if (ena_link)
+ pi->phy.curr_user_phy_cfg.caps |= ICE_AQC_PHY_EN_LINK;
+ else
+ pi->phy.curr_user_phy_cfg.caps &= ~ICE_AQC_PHY_EN_LINK;
+
+ return ICE_SUCCESS;
}
/**
@@ -1057,11 +1057,11 @@ ice_sched_add_nodes_to_layer(struct ice_port_info *pi,
u32 *first_teid_ptr = first_node_teid;
u16 new_num_nodes = num_nodes;
enum ice_status status = ICE_SUCCESS;
+ u32 temp;
*num_nodes_added = 0;
while (*num_nodes_added < num_nodes) {
u16 max_child_nodes, num_added = 0;
- u32 temp;
status = ice_sched_add_nodes_to_hw_layer(pi, tc_node, parent,
layer, new_num_nodes,
@@ -2520,7 +2520,7 @@ ice_free_sw_marker_lg(struct ice_hw *hw, u16 marker_lg_id, u32 sw_marker)
return ICE_ERR_NO_MEMORY;
sw_buf->num_elems = CPU_TO_LE16(num_elems);
- if (sw_marker == (sw_marker & 0xFFFF))
+ if (sw_marker <= 0xFFFF)
sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_WIDE_TABLE_1);
else
sw_buf->res_type = CPU_TO_LE16(ICE_AQC_RES_TYPE_WIDE_TABLE_2);
@@ -4299,9 +4299,9 @@ enum ice_status ice_update_sw_rule_bridge_mode(struct ice_hw *hw)
{
struct ice_fltr_mgmt_list_entry *fm_entry;
enum ice_status status = ICE_SUCCESS;
+ struct ice_switch_info *sw = NULL;
struct LIST_HEAD_TYPE *rule_head;
struct ice_lock *rule_lock; /* Lock to protect filter rule list */
- struct ice_switch_info *sw;
sw = hw->switch_info;
rule_lock = &sw->recp_list[ICE_SW_LKUP_MAC].filt_rule_lock;
@@ -5545,7 +5545,7 @@ ice_cfg_dflt_vsi(struct ice_port_info *pi, u16 vsi_handle, bool set,
u8 direction)
{
struct ice_fltr_list_entry f_list_entry;
- struct ice_sw_recipe *recp_list;
+ struct ice_sw_recipe *recp_list = NULL;
struct ice_fltr_info f_info;
struct ice_hw *hw = pi->hw;
enum ice_status status;
@@ -8698,6 +8698,36 @@ ice_fill_adv_packet_tun(struct ice_hw *hw, enum ice_sw_tunnel_type tun_type,
return ICE_ERR_CFG;
}
+/**
+ * ice_fill_adv_packet_vlan - fill dummy packet with VLAN tag type
+ * @vlan_type: VLAN tag type
+ * @pkt: dummy packet to fill in
+ * @offsets: offset info for the dummy packet
+ */
+static enum ice_status
+ice_fill_adv_packet_vlan(u16 vlan_type, u8 *pkt,
+ const struct ice_dummy_pkt_offsets *offsets)
+{
+ u16 i;
+
+ /* Find VLAN header and insert VLAN TPID */
+ for (i = 0; offsets[i].type != ICE_PROTOCOL_LAST; i++) {
+ if (offsets[i].type == ICE_VLAN_OFOS ||
+ offsets[i].type == ICE_VLAN_EX) {
+ struct ice_vlan_hdr *hdr;
+ u16 offset;
+
+ offset = offsets[i].offset;
+ hdr = (struct ice_vlan_hdr *)&pkt[offset];
+ hdr->type = CPU_TO_BE16(vlan_type);
+
+ return ICE_SUCCESS;
+ }
+ }
+
+ return ICE_ERR_CFG;
+}
+
/**
* ice_find_adv_rule_entry - Search a rule entry
* @hw: pointer to the hardware structure
@@ -9131,7 +9161,7 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
ICE_SINGLE_ACT_Q_REGION_M;
break;
case ICE_SET_MARK:
- if (rinfo->sw_act.markid != (rinfo->sw_act.markid & 0xFFFF))
+ if (rinfo->sw_act.markid > 0xFFFF)
nb_lg_acts_mark += 1;
/* Allocate a hardware table entry to hold large act. */
status = ice_alloc_res_lg_act(hw, &lg_act_id, nb_lg_acts_mark);
@@ -9184,6 +9214,14 @@ ice_add_adv_rule(struct ice_hw *hw, struct ice_adv_lkup_elem *lkups,
goto err_ice_add_adv_rule;
}
+ if (rinfo->vlan_type != 0 && ice_is_dvm_ena(hw)) {
+ status = ice_fill_adv_packet_vlan(rinfo->vlan_type,
+ s_rule->hdr_data,
+ pkt_offsets);
+ if (status)
+ goto err_ice_add_adv_rule;
+ }
+
rx_tx = s_rule;
if (rinfo->sw_act.fltr_act == ICE_SET_MARK) {
lg_act_sz = (u16)ice_struct_size(lg_rule, act, nb_lg_acts_mark);
@@ -9752,7 +9790,7 @@ enum ice_status
ice_replay_vsi_all_fltr(struct ice_hw *hw, struct ice_port_info *pi,
u16 vsi_handle)
{
- struct ice_switch_info *sw;
+ struct ice_switch_info *sw = NULL;
enum ice_status status;
u8 i;
@@ -207,19 +207,19 @@ struct ice_adv_lkup_elem {
union ice_prot_hdr m_u; /* Mask of header values to match */
};
-struct lg_entry_vsi_fwd {
+struct entry_vsi_fwd {
u16 vsi_list;
u8 list;
u8 valid;
};
-struct lg_entry_to_q {
+struct entry_to_q {
u16 q_idx;
u8 q_region_sz;
u8 q_pri;
};
-struct lg_entry_prune {
+struct entry_prune {
u16 vsi_list;
u8 list;
u8 egr;
@@ -227,28 +227,29 @@ struct lg_entry_prune {
u8 prune_t;
};
-struct lg_entry_mirror {
+struct entry_mirror {
u16 mirror_vsi;
};
-struct lg_entry_generic_act {
+struct entry_generic_act {
u16 generic_value;
u8 offset;
u8 priority;
};
-struct lg_entry_statistics {
+struct entry_statistics {
u8 counter_idx;
};
union lg_act_entry {
- struct lg_entry_vsi_fwd vsi_fwd;
- struct lg_entry_to_q to_q;
- struct lg_entry_prune prune;
- struct lg_entry_mirror mirror;
- struct lg_entry_generic_act generic_act;
- struct lg_entry_statistics statistics;
+ struct entry_vsi_fwd vsi_fwd;
+ struct entry_to_q to_q;
+ struct entry_prune prune;
+ struct entry_mirror mirror;
+ struct entry_generic_act generic_act;
+ struct entry_statistics statistics;
};
+
struct ice_prof_type_entry {
u16 prof_id;
enum ice_sw_tunnel_type type;
@@ -301,6 +302,7 @@ struct ice_adv_rule_info {
u8 rx; /* true means LOOKUP_RX otherwise LOOKUP_TX */
u16 fltr_rule_id;
u16 lg_id;
+ u16 vlan_type;
struct ice_adv_rule_flags_info flags_info;
};
@@ -693,9 +693,11 @@ struct ice_hw_common_caps {
bool sec_rev_disabled;
bool update_disabled;
bool nvm_unified_update;
+ bool netlist_auth;
#define ICE_NVM_MGMT_SEC_REV_DISABLED BIT(0)
#define ICE_NVM_MGMT_UPDATE_DISABLED BIT(1)
#define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
+#define ICE_NVM_MGMT_NETLIST_AUTH_SUPPORT BIT(5)
/* PCIe reset avoidance */
bool pcie_reset_avoidance; /* false: not supported, true: supported */
/* Post update reset restriction */
@@ -1458,6 +1460,7 @@ enum ice_sw_fwd_act_type {
ICE_FWD_TO_QGRP,
ICE_SET_MARK,
ICE_DROP_PACKET,
+ ICE_LG_ACTION,
ICE_INVAL_ACT
};