From: Srujana Challa <schalla@marvell.com>
Updates CPT inbound inline configuration mailbox message
format to set CPT credit threshold and bpid, which are
introduced for CN10KB.
This patch also fixes inline inbound config read API.
Fixes: 37da58509579 ("common/cnxk: update inbound inline IPsec config mailbox")
Cc: schalla@marvell.com
Signed-off-by: Srujana Challa <schalla@marvell.com>
---
drivers/common/cnxk/roc_cpt.c | 14 +++++++++++++-
drivers/common/cnxk/roc_cpt.h | 14 ++++++++++++--
drivers/common/cnxk/roc_mbox.h | 6 +++++-
3 files changed, 30 insertions(+), 4 deletions(-)
@@ -268,9 +268,10 @@ roc_cpt_inline_ipsec_cfg(struct dev *cpt_dev, uint8_t lf_id,
int
roc_cpt_inline_ipsec_inb_cfg_read(struct roc_cpt *roc_cpt,
- struct nix_inline_ipsec_cfg *inb_cfg)
+ struct roc_cpt_inline_ipsec_inb_cfg *cfg)
{
struct cpt *cpt = roc_cpt_to_cpt_priv(roc_cpt);
+ struct nix_inline_ipsec_cfg *inb_cfg;
struct dev *dev = &cpt->dev;
struct mbox *mbox = mbox_get(dev->mbox);
struct msg_req *req;
@@ -283,6 +284,17 @@ roc_cpt_inline_ipsec_inb_cfg_read(struct roc_cpt *roc_cpt,
}
rc = mbox_process_msg(mbox, (void *)&inb_cfg);
+ if (rc) {
+ rc = -EIO;
+ goto exit;
+ }
+ cfg->cpt_credit = inb_cfg->cpt_credit;
+ cfg->egrp = inb_cfg->gen_cfg.egrp;
+ cfg->opcode = inb_cfg->gen_cfg.opcode;
+ cfg->param1 = inb_cfg->gen_cfg.param1;
+ cfg->param2 = inb_cfg->gen_cfg.param2;
+ cfg->bpid = inb_cfg->bpid;
+ cfg->credit_th = inb_cfg->credit_th;
exit:
mbox_put(mbox);
return rc;
@@ -144,6 +144,16 @@ struct roc_cpt_rxc_time_cfg {
uint16_t zombie_thres;
};
+struct roc_cpt_inline_ipsec_inb_cfg {
+ uint32_t cpt_credit;
+ uint16_t opcode;
+ uint16_t param1;
+ uint16_t param2;
+ uint16_t bpid;
+ uint32_t credit_th;
+ uint8_t egrp;
+};
+
int __roc_api roc_cpt_rxc_time_cfg(struct roc_cpt *roc_cpt,
struct roc_cpt_rxc_time_cfg *cfg);
int __roc_api roc_cpt_dev_init(struct roc_cpt *roc_cpt);
@@ -159,8 +169,8 @@ int __roc_api roc_cpt_lf_ctx_flush(struct roc_cpt_lf *lf, void *cptr,
int __roc_api roc_cpt_lf_ctx_reload(struct roc_cpt_lf *lf, void *cptr);
int __roc_api roc_cpt_inline_ipsec_cfg(struct dev *dev, uint8_t slot,
struct roc_nix *nix);
-int __roc_api roc_cpt_inline_ipsec_inb_cfg_read(
- struct roc_cpt *roc_cpt, struct nix_inline_ipsec_cfg *inb_cfg);
+int __roc_api roc_cpt_inline_ipsec_inb_cfg_read(struct roc_cpt *roc_cpt,
+ struct roc_cpt_inline_ipsec_inb_cfg *cfg);
int __roc_api roc_cpt_inline_ipsec_inb_cfg(struct roc_cpt *roc_cpt,
uint16_t param1, uint16_t param2,
uint16_t opcode);
@@ -266,7 +266,7 @@ struct mbox_msghdr {
msg_rsp) \
M(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp) \
M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \
- msg_req, nix_inline_ipsec_cfg) \
+ msg_req, nix_inline_ipsec_cfg) \
M(NIX_LF_INLINE_RQ_CFG, 0x8024, nix_lf_inline_rq_cfg, \
nix_rq_cpt_field_mask_cfg_req, msg_rsp) \
M(NIX_SPI_TO_SA_ADD, 0x8026, nix_spi_to_sa_add, nix_spi_to_sa_add_req, \
@@ -1198,6 +1198,8 @@ struct nix_inline_ipsec_cfg {
uint8_t __io cpt_slot;
} inst_qsel;
uint8_t __io enable;
+ uint16_t __io bpid;
+ uint32_t __io credit_th;
};
/* Per NIX LF inline IPSec configuration */
@@ -1503,6 +1505,8 @@ struct cpt_rx_inline_lf_cfg_msg {
uint16_t __io param2;
uint16_t __io opcode;
uint32_t __io credit;
+ uint32_t __io credit_th;
+ uint16_t __io bpid;
uint32_t __io reserved;
};